From 8d4bb94663eb89b6cc14d16f6cc3f06439752217 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Sat, 26 Jul 2025 09:20:06 +0200
Subject: [PATCH] sb/intel/common/gpio: Add and use gpio_invert()

Introduce a new helper function to set the INVERT bits on
the first GPIO bank. Use it on google link instead of using
a custom implementation.

Change-Id: Icfdbc3dcae5678695b6fcc9dab7ff97d291963cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88565
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/link/mainboard.c |  8 +-------
 src/southbridge/intel/common/gpio.c   | 16 ++++++++++++++++
 src/southbridge/intel/common/gpio.h   |  4 ++++
 3 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index c31ab110a2..c6f357bcdf 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -114,13 +114,7 @@ static void mainboard_init(struct device *dev)
 	google_chromeec_get_board_version(&board_version);
 	if (board_version == 0) {
 		/* If running on proto1 - enable reversion of gpio11. */
-		u32 gpio_inv;
-		u16 gpio_base = pci_read_config16
-			(pcidev_on_root(0x1f, 0), GPIO_BASE) &
-			0xfffc;
-		u16 gpio_inv_addr = gpio_base + GPI_INV;
-		gpio_inv = inl(gpio_inv_addr);
-		outl(gpio_inv | (1 << 11), gpio_inv_addr);
+		gpio_invert(11, true);
 	}
 }
 
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index a1b2b5426b..681457d51c 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -222,3 +222,19 @@ void gpio_output(gpio_t gpio_num, int value)
 	/* Set value again in case output register was gated */
 	gpio_set(gpio_num, value);
 }
+
+void gpio_invert(gpio_t gpio_num, bool invert)
+{
+	u16 gpio_blink_reg = get_gpio_base() + GPI_INV;
+	u32 config;
+
+	if (gpio_num >= 32)
+		return; /* Just ignore wrong gpio numbers. */
+
+	config = inl(gpio_blink_reg);
+	if (invert)
+		config |= BIT(gpio_num);
+	else
+		config &= ~BIT(gpio_num);
+	outl(gpio_blink_reg, config);
+}
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 71154a6066..4502d8f157 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -4,6 +4,7 @@
 #define INTEL_COMMON_GPIO_H
 
 #include <stdint.h>
+#include <stdbool.h>
 #include <soc/gpio.h>
 
 /* ICH7 GPIOBASE */
@@ -153,4 +154,7 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio);
 
 int gpio_is_native(int gpio_num);
 
+/* Enable/disable GPI_INV for the specified GPIO */
+void gpio_invert(gpio_t gpio_num, bool invert);
+
 #endif