From 8d2df573a8d2e4821136a88295c062c37195115e Mon Sep 17 00:00:00 2001 From: Swathi Tamilselvan Date: Wed, 20 Aug 2025 14:59:35 +0530 Subject: [PATCH] soc/qualcomm/x1p42100/qclib: Support to pack and load CPR binary in CBFS CPR image is required by Qclib for PMIC initialization. This patch adds support to pack and load the CPR binary, reserves memory for CPR settings in the memory layout and adds CPR entry in if_table which is passed to Qclib. TEST=1. Create an image.serial.bin and ensure it boots on X1P42100. 2. Verified using CPR load log from coreboot. ``` [INFO ] CBFS: Found 'fallback/cpr' @0xa3900 size 0x46d in mcache @0x1485e340 [INFO ] VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not supported for secdata_kernel v0, return 0 [INFO ] VB2:vb2_digest_init() 1133 bytes, hash algo 2, HW acceleration forbidden [INFO ] CBFS: Found 'fallback/shrm_meta' @0xebb80 size 0xb0d in mcache @0x1485e7c0 ``` Change-Id: I58161a1d05222c84e077ada1024db50440e783f1 Signed-off-by: Swathi Tamilselvan Reviewed-on: https://review.coreboot.org/c/coreboot/+/88870 Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/soc/qualcomm/x1p42100/Makefile.mk | 8 ++++++++ src/soc/qualcomm/x1p42100/memlayout.ld | 1 + src/soc/qualcomm/x1p42100/qclib.c | 8 ++++++++ 3 files changed, 17 insertions(+) diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk index 36d2578cf5..c483b5f691 100644 --- a/src/soc/qualcomm/x1p42100/Makefile.mk +++ b/src/soc/qualcomm/x1p42100/Makefile.mk @@ -120,6 +120,14 @@ $(DTB_CBFS)-type := raw $(DTB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(DTB_CBFS) +################################################################################ +CPR_FILE := $(X1P42100_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/cpr.bin +CPR_CBFS := $(CONFIG_CBFS_PREFIX)/cpr +$(CPR_CBFS)-file := $(CPR_FILE) +$(CPR_CBFS)-type := raw +$(CPR_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(CPR_CBFS) + ################################################################################ UART_FW_FILE := $(X1P42100_BLOB)/qup_fw/uart_fw.bin UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld index 4154534f2b..b543c51c1e 100644 --- a/src/soc/qualcomm/x1p42100/memlayout.ld +++ b/src/soc/qualcomm/x1p42100/memlayout.ld @@ -36,6 +36,7 @@ SECTIONS REGION(qc_blob_meta, 0x14888000, 16K, 4K) REGION(aop_blob_meta, 0x1488c000, 16K, 4K) REGION(qclib, 0x14897000, 1536K, 4K) + REGION(cpr_settings, 0x14A17000, 12K, 4K) PRERAM_CBMEM_CONSOLE(0x14A30000, 32K) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K) REGION(auth_metadata,0x14A7D000 , 8K, 4K) diff --git a/src/soc/qualcomm/x1p42100/qclib.c b/src/soc/qualcomm/x1p42100/qclib.c index 961f822a4f..ea1424c402 100644 --- a/src/soc/qualcomm/x1p42100/qclib.c +++ b/src/soc/qualcomm/x1p42100/qclib.c @@ -19,6 +19,14 @@ int qclib_soc_override(struct qclib_cb_if_table *table) } qclib_add_if_table_entry(QCLIB_TE_DTB_SETTINGS, _dtb, data_size, 0); + /* Attempt to load CPR Blob */ + data_size = cbfs_load(qclib_file(QCLIB_CBFS_CPR), _cpr_settings, REGION_SIZE(cpr_settings)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /cpr failed\n", __func__); + return -1; + } + qclib_add_if_table_entry(QCLIB_TE_CPR_SETTINGS, _cpr_settings, data_size, 0); + /* Attempt to load shrm_meta Blob */ data_size = cbfs_load(qclib_file(QCLIB_CBFS_SHRM_META), _qc_blob_meta, REGION_SIZE(qc_blob_meta));