From 8c717df03a4a21b2cad77f15255759382c7319b6 Mon Sep 17 00:00:00 2001 From: Appukuttan V K Date: Thu, 28 Aug 2025 12:31:06 +0530 Subject: [PATCH] soc/intel/ptl: Update Wildcat Lake PCIe root port numbering MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit updates the PCIe root port numbering for Wildcat Lake as per the revised EDS document. This update ensures alignment with the PCIe root port architecture. Current: - Bus-Device-Function: 0h – 6h – 0h = Root Port 5 - Bus-Device-Function: 0h – 6h – 1h = Root Port 6 New: - Bus-Device-Function: 0h – 6h – 0h = Root Port 9 - Bus-Device-Function: 0h – 6h – 1h = Root Port 10 This resolves the warning shown during PCIe enumeration in boot logs. References: - Wildcat Lake Platform Message of the Week (#844458) - Wildcat Lake Processor EDS Volume 1 (#842271) - Wildcat Lake External Design Specification (EDS) Volume 2 (#829345) BUG=b:433687705 TEST=Boot the system with the updated firmware and verify that below warning is not reported for the PCIe root ports: "[WARN ] pcie_rp_original_idx: Unexpected root-port number '9' at PCI: 00:06.0, ignoring." Change-Id: Icf5e3ae3d008f8d79480959bef7b4768fb34b4a8 Signed-off-by: Appukuttan V K Reviewed-on: https://review.coreboot.org/c/coreboot/+/88980 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N Reviewed-by: Usha P --- src/soc/intel/pantherlake/pcie_rp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index cacbab83ad..35702391e2 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -25,6 +25,8 @@ static const struct pcie_rp_group ptl_rp_groups[] = { #endif #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) { .slot = PCI_DEV_SLOT_PCIE_2, .count = 4, .lcap_port_base = 1 }, +#elif CONFIG(SOC_INTEL_WILDCATLAKE) + { .slot = PCI_DEV_SLOT_PCIE_2, .count = 2, .lcap_port_base = 5 }, #else { .slot = PCI_DEV_SLOT_PCIE_2, .count = 2, .lcap_port_base = 1 }, #endif