tree: Use boolean for "eist_enable"

Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>

src/mainboard/51nb/x210/devicetree.cb

@@ -16,7 +16,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/acer/aspire_vn7_572g/devicetree.cb

@@ -36,7 +36,7 @@ chip soc/intel/skylake
 		subsystemid 0x1025 0x1037 inherit
 		device ref system_agent	on
 			# Enable "Enhanced Intel SpeedStep"
-			register "eist_enable" = "1"
+			register "eist_enable" = "true"
 
 			# Set the Thermal Control Circuit (TCC) activation value to 97C
 			# even though FSP integration guide says to set it to 100C for SKL-U

src/mainboard/asrock/h110m/devicetree.cb

@@ -4,7 +4,7 @@ chip soc/intel/skylake
 
 	register "deep_sx_config" = "DSX_EN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb

@@ -17,7 +17,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb

@@ -16,7 +16,7 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s

src/mainboard/facebook/monolith/devicetree.cb

@@ -19,7 +19,7 @@ chip soc/intel/skylake
 	register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"
 
 	# "Intel SpeedStep Technology"
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# DPTF
 	register "dptf_enable" = "1"

src/mainboard/google/eve/devicetree.cb

@@ -19,7 +19,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/google/fizz/variants/baseboard/devicetree.cb

@@ -16,7 +16,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Mapping of USB port # to device
 	#+----------------+-------+-----------------------------------+

src/mainboard/google/poppy/variants/nocturne/devicetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/hp/280_g2/devicetree.cb

@@ -5,7 +5,7 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,	/* Routed to debug header */
 	}"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	device domain 0 on
 		subsystemid 0x103c 0x2b5e inherit

src/mainboard/lenovo/m900_tiny/devicetree.cb

@@ -6,7 +6,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/libretrend/lt1000/devicetree.cb

@@ -7,7 +7,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Set the Thermal Control Circuit (TCC) activation value to 95C
 	# even though FSP integration guide says to set it to 100C for SKL-U

src/mainboard/msi/ms7d25/devicetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/alderlake
 	# FSP configuration
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"

src/mainboard/msi/ms7e06/devicetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/alderlake
 	# FSP configuration
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Sagv Configuration
 	register "sagv" = "SaGv_Enabled"

src/mainboard/prodrive/hermes/devicetree.cb

@@ -108,7 +108,7 @@ chip soc/intel/cannonlake
 	register "s0ix_enable" = "0"
 
 	# Enable Turbo
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	register "common_soc_config" = "{
 		.gspi[0] = {

src/mainboard/protectli/vault_cml/devicetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	register "cpu_pl2_4_cfg" = "baseline"
 

src/mainboard/protectli/vault_ehl/devicetree.cb

@@ -8,7 +8,7 @@ chip soc/intel/elkhartlake
 	}"
 
 	register "SaGv" = "SaGv_Enabled"
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Enable lpss s0ix
 	register "s0ix_enable" = "1"

src/mainboard/protectli/vault_kbl/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/skylake
 	register "gpe0_dw1" = "GPP_D"
 	register "gpe0_dw2" = "GPP_E"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Disable DPTF
 	register "dptf_enable" = "0"

src/mainboard/purism/librem_cnl/devicetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/cannonlake
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/purism/librem_jsl/devicetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/jasperlake
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 	register "s0ix_enable" = "0"
 
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/purism/librem_l1um_v2/devicetree.cb

@@ -21,7 +21,7 @@ chip soc/intel/cannonlake
 
 	register "s0ix_enable" = "0"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,

src/mainboard/purism/librem_skl/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "0"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Set the Thermal Control Circuit (TCC) activaction value to 95C
 	# even though FSP integration guide says to set it to 100C for SKL-U

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -5,7 +5,7 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "0"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/starlabs/starbook/variants/adl/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/alderlake
 	register "sagv"				= "SaGv_Enabled"
 
 	# FSP Silicon
-	register "eist_enable"			= "1"
+	register "eist_enable"			= "true"
 
 	# Serial I/O
 	register "serial_io_i2c_mode" = "{

src/mainboard/starlabs/starbook/variants/cml/devicetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/cannonlake
 	# CPU
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable"			= "1"
+	register "eist_enable"			= "true"
 
 	# Graphics
 	# IGD Displays

src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/skylake
 # CPU
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable"			= "1"
+	register "eist_enable"			= "true"
 
 	# Graphics
 	# IGD Displays

src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/tigerlake
 # CPU
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable"			= "1"
+	register "eist_enable"			= "true"
 
 	# Graphics
 	# Not used but timings left for reference

src/mainboard/system76/addw1/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"

src/mainboard/system76/adl/devicetree.cb

@@ -11,7 +11,7 @@ chip soc/intel/alderlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"

src/mainboard/system76/bonw14/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"

src/mainboard/system76/cml-u/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"

src/mainboard/system76/gaze15/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"

src/mainboard/system76/kbl-u/devicetree.cb

@@ -11,7 +11,7 @@ chip soc/intel/skylake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Serial I/O
 	register "SerialIoDevMode" = "{

src/mainboard/system76/oryp5/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"

src/mainboard/system76/oryp6/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"

src/mainboard/system76/rpl/devicetree.cb

@@ -11,7 +11,7 @@ chip soc/intel/alderlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"

src/mainboard/system76/tgl-h/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/tigerlake
 
 # ACPI (soc/intel/tigerlake/acpi.c)
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # CPU (soc/intel/tigerlake/cpu.c)
 	# Power limits

src/mainboard/system76/tgl-u/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/tigerlake
 
 # ACPI (soc/intel/tigerlake/acpi.c)
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 	# Enable s0ix, required for TGL-U
 	register "s0ix_enable" = "1"

src/mainboard/system76/whl-u/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
+	register "eist_enable" = "true"
 
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"

src/soc/intel/alderlake/chip.h

@@ -467,7 +467,7 @@ struct soc_intel_alderlake_config {
 
 	bool skip_ext_gfx_scan;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
 	bool eist_enable;
 
 	/* Enable C6 DRAM */

src/soc/intel/cannonlake/chip.h

@@ -237,7 +237,7 @@ struct soc_intel_cannonlake_config {
 	/* Enables support for Teton Glacier hybrid storage device */
 	bool TetonGlacierMode;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
 	bool eist_enable;
 
 	/* Enable C6 DRAM */

src/soc/intel/elkhartlake/chip.h

@@ -258,8 +258,8 @@ struct soc_intel_elkhartlake_config {
 	uint8_t Heci2Enable;
 	uint8_t Heci3Enable;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
-	uint8_t eist_enable;
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
+	bool eist_enable;
 
 	/*
 	 * SerialIO device mode selection:

src/soc/intel/jasperlake/chip.h

@@ -178,7 +178,7 @@ struct soc_intel_jasperlake_config {
 	/* Gfx related */
 	bool SkipExtGfxScan;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
 	bool eist_enable;
 
 	/* Enable C6 DRAM */

src/soc/intel/skylake/chip.h

@@ -459,8 +459,8 @@ struct soc_intel_skylake_config {
 	u8 SlowSlewRateForSa;
 
 	/* Enable/Disable EIST
-	 * 1b - Enabled
-	 * 0b - Disabled
+	 * true - Enabled
+	 * false - Disabled
 	 */
 	bool eist_enable;
 

src/soc/intel/tigerlake/chip.h

@@ -286,8 +286,8 @@ struct soc_intel_tigerlake_config {
 	/* Gfx related */
 	uint8_t SkipExtGfxScan;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
-	uint8_t eist_enable;
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
+	bool eist_enable;
 
 	/* Enable C6 DRAM */
 	uint8_t enable_c6dram;