From 8c46232005767ecbdebb7290f15cacf2756c9586 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 29 Nov 2022 15:45:06 -0800 Subject: [PATCH] soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. BUG=b:235863379 TEST=Boot in compliance mode, check FSP settings Signed-off-by: Bora Guvendik Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/alderlake/fsp_params.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 853b2f2c0d..224cf8a9ea 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -471,7 +471,9 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) */ static int get_l1_substate_control(enum L1_substates_control ctl) { - if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) + ctl = L1_SS_DISABLED; + else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) ctl = L1_SS_L1_2; return ctl - 1; }