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armv7/exynos5420: Provide configuration for SPI0~SPI2.

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Fill the SPI device parameters for spi_setup_slave on Exynos 5420.

BUG=chrome-os-partner:20441
TEST=emerge-peach_pit chromeos-coreboot-peach_pit
BRANCH=peach_pit

Change-Id: I447e877332451a0172e2530f3f127343f8a730c3
Reviewed-on: https://gerrit.chromium.org/gerrit/60082
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Hung-Te Lin 2013-06-26 20:17:42 +08:00 • committed by ChromeBot
commit 8c12f46b7c
1 changed files with 29 additions and 4 deletions
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33
src/cpu/samsung/exynos5420/spi.c
View file

@ -41,6 +41,32 @@ struct exynos_spi_slave {
uint8_t frame_header; /* header byte to detect in half-duplex mode. */
};
/* TODO(hungte) Move the SPI param list to per-board configuration, probably
* Kconfig or mainboard.c */
static struct exynos_spi_slave exynos_spi_slaves[3] = {
// SPI 0
{
.slave = { .bus = 0, },
.regs = samsung_get_base_spi0(),
},
// SPI 1
{
.slave = { .bus = 1, .rw = SPI_READ_FLAG, },
.regs = samsung_get_base_spi1(),
.fifo_size = 64,
.half_duplex = 0,
},
// SPI 2
{
.slave = { .bus = 2,
.rw = SPI_READ_FLAG | SPI_WRITE_FLAG, },
.regs = samsung_get_base_spi2(),
.fifo_size = 64,
.half_duplex = 1,
.frame_header = 0xec,
},
};
static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
{
return container_of(slave, struct exynos_spi_slave, slave);
@ -54,14 +80,13 @@ void spi_init(void)
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
// TODO(hungte) Provide Exynos SPI device setup.
return NULL;
ASSERT(bus >= 0 && bus < 3);
return &(exynos_spi_slaves[bus].slave);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
// TODO(hungte) Detect and check if BUS/CS is valid.
return 0;
return bus > 0 && bus < 3;
}
void spi_cs_activate(struct spi_slave *slave)