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UPSTREAM: quark: Enable HSUART0 as console

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The use of HSUART0 on galileo requires early initialization of the I2C
GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1
on the expansion connector.

TEST=None

Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15010
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit bc518d5cab)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348425
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Lee Leahy 2016-05-30 15:01:06 -07:00 • committed by chrome-bot
commit 8bae1e76e0
7 changed files with 126 additions and 27 deletions
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50
src/mainboard/intel/galileo/gen1.h
View file

@ -59,6 +59,56 @@ static const struct reg_script gen1_gpio_init[] = {
REG_SCRIPT_END
};
static const struct reg_script gen1_hsuart0_0x20[] = {
/* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
* Set IO1_MUX (EXP.PORT3_5) output, low
* Set LVL_OE (GPIO_SUS2) output, high
*/
REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
/* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
* Set IO0_MUX (EXP.PORT3_4) output, low
* Set LVL_OE (GPIO_SUS2) output, high
*/
REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
REG_SCRIPT_END
};
static const struct reg_script gen1_hsuart0_0x21[] = {
/* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
* Set IO1_MUX (EXP.PORT3_5) output, low
* Set LVL_OE (GPIO_SUS2) output, high
*/
REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
/* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
* Set IO0_MUX (EXP.PORT3_4) output, low
* Set LVL_OE (GPIO_SUS2) output, high
*/
REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
REG_SCRIPT_END
};
static const struct reg_script gen1_i2c_0x20_init[] = {
/* Route I2C pins to Arduino header:
* Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector

22
src/mainboard/intel/galileo/gen2.h
View file

@ -52,6 +52,28 @@ static const struct reg_script gen2_gpio_init[] = {
REG_SCRIPT_END
};
static const struct reg_script gen2_hsuart0[] = {
/* Route UART0_TXD to MUX7_Y -> BUF_IO1 -> IO1 -> DIGITAL 1
* Set MUX7_SEL (EXP1.P1_5) high
* Configure MUX7_SEL (EXP1.P1_5) as an output
* Set LVL_B_OE6_N (EXP0.P1_4) low
* Configure LVL_B_OE6_N (EXP0.P1_4) as an output
*/
REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, BIT5),
REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT5),
REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
/* Route DIGITAL 0 -> IO0 -> UART0_RXD
* Set LVL_C_OE0_N (EXP1.P0_0) high
* Configure LVL_C_OE0_N (EXP1.P0_0) as an output
*/
REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT0, BIT0),
REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG0, ~BIT0),
REG_SCRIPT_END
};
static const struct reg_script gen2_i2c_init[] = {
/* Route I2C to Arduino Shield connector:
* Set AMUX1_IN (EXP2.P1_4) low

38
src/mainboard/intel/galileo/gpio.c
View file

@ -15,11 +15,35 @@
#include <arch/io.h>
#include <console/console.h>
#include <fsp/romstage.h>
#include <soc/ramstage.h>
#include "reg_access.h"
#include "gen1.h"
#include "gen2.h"
void car_mainboard_pre_console_init(void)
{
const struct reg_script *script;
/* Initialize the GPIO controllers */
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
script = gen2_gpio_init;
else
script = gen1_gpio_init;
reg_script_run(script);
/* Initialize the RXD and TXD paths for UART0 */
if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) {
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
script = gen2_hsuart0;
else
script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
? gen1_hsuart0_0x21 : gen1_hsuart0_0x20;
reg_script_run(script);
}
}
void mainboard_gpio_i2c_init(device_t dev)
{
const struct reg_script *script;
@ -33,24 +57,12 @@ void mainboard_gpio_i2c_init(device_t dev)
/* Determine which I2C address is in use */
script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
? gen1_i2c_0x21_init : gen1_i2c_0x20_init;
/* Initialize the I2C chips */
reg_script_run(script);
}
void mainboard_gpio_init(void)
{
const struct reg_script *script;
/* Initialize the GPIO controllers */
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
script = gen2_gpio_init;
else
script = gen1_gpio_init;
reg_script_run(script);
}
void mainboard_gpio_pcie_reset(uint32_t pin_value)
{
uint32_t pin_number;