Support for tnt-2 based motherboards.
This commit is contained in:
Ronald G. Minnich
parent
e19dec0057
commit
8b8b2fe3fb
8 changed files with 497 additions and 408 deletions
13
src/mainboard/pcchips/m754lmr/Config
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13
src/mainboard/pcchips/m754lmr/Config
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@ -0,0 +1,13 @@
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arch i386
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northbridge acer/m1631
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southbridge acer/m1535
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superio acer/m1535
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option ENABLE_FIXED_AND_VARIABLE_MTRRS
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option FINAL_MAINBOARD_FIXUP
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option HAVE_PIRQ_TABLE
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object mainboard.o
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object irq_tables.o
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keyboard pc80
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cpu p5
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cpu p6
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1
src/mainboard/pcchips/m754lmr/README
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1
src/mainboard/pcchips/m754lmr/README
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@ -0,0 +1 @@
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This mainboard uses the Acer Aladdin TNT2 chipset.
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31
src/mainboard/pcchips/m754lmr/irq_tables.c
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31
src/mainboard/pcchips/m754lmr/irq_tables.c
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@ -0,0 +1,31 @@
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#include <i386_subr.h>
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/* NOTE -- THIS IS A PLACEHOLDER -- WE NEED TO FIX THIS */
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#define CHECKSUM 0xe6
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*5, /* there can be total 5 devices on the bus */
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0x00, /* Bus 0 */
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0x08, /* Device 1, Function 0 */
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0x0A20, /* reserve IRQ 11, 9, 5, for PCI */
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0x1039, /* Silicon Integrated System */
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0x0008, /* SiS 85C503/5513 ISA Bridge */
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0x00, /* u8 miniport_data - "crap" */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
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{
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/* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, 0x58, {{0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}},
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0x01, 0x00},
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{0x00, 0x60, {{0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}},
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0x02, 0x00},
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{0x00, 0x01, {{0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}},
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0x00, 0x00},
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{0x00, 0x10, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
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0x00, 0x00},
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{0x00, 0x0a, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
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0x00, 0x00},
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}
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};
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17
src/mainboard/pcchips/m754lmr/mainboard.c
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17
src/mainboard/pcchips/m754lmr/mainboard.c
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@ -0,0 +1,17 @@
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#include <printk.h>
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#include <pci.h>
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#include <cpu/p5/io.h>
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void mainboard_fixup()
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{
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printk("mainboard_fixup()\n");
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}
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void final_mainboard_fixup()
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{
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void final_northbridge_fixup(void);
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final_northbridge_fixup();
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}
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@ -14,24 +14,27 @@ register_table:
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.byte 0x58, 0x00, 0x40
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.byte 0x59, 0x00, 0x40
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.byte 0x61, 0x00, 0x00
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.byte 0x62, 0x00, 0x80
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.byte 0x62, 0x00, 0x01 /* 0x80 */
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.byte 0x63, 0x00, 0x08
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.byte 0x67, 0xff, 0x08
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.byte 0x67, 0xff, 0x09 /*0x08*/
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#ifndef USE_DOC_MIL
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.byte 0x6c, 0xfc, 0x00
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.byte 0x6d, 0xd7, 0x00 /* probably wrong OR value?*/
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.byte 0x6f, 0xff, 0x40
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.byte 0x6c, 0xfc, 0x00
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.byte 0x6d, 0xd7, 0x00 /* probably wrong OR value?*/
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.byte 0x6f, 0xff, 0x40
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#endif
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.byte 0x70, 0xfc, 0x00
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.byte 0x74, 0xfc, 0x00
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.byte 0x71, 0xd7, 0x00 /* probably wrong OR value?*/
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.byte 0x75, 0xd7, 0x00 /* probably wrong OR value?*/
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/* .byte 0x70, 0xfc, 0x00 */
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/* .byte 0x74, 0xfc, 0x00 */
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# .byte 0x71, 0xd7, 0x00 /* probably wrong OR value?*/
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# .byte 0x75, 0xd7, 0x00 /* probably wrong OR value?*/
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.byte 0x73, 0xff, 0x40
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.byte 0x77, 0xff, 0x40
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.byte 0x7c, 0x00, 0x11 /* MCLK = 66 MHZ */
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.byte 0x7d, 0x00, 0xc4 /* MCLK = 66 MHZ */
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.byte 0x7e, 0x03, 0x28
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.byte 0x7f, 0xef, 0x24
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# .byte 0x7c, 0x00, 0x11 /* MCLK = 66 MHZ */
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# .byte 0x7d, 0x00, 0xc4 /* MCLK = 66 MHZ */
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# .byte 0x7e, 0x03, 0x28
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.byte 0x91, 0x00, 0x70 /*cheng 0629 add for test*/
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.byte 0x7f, 0xef, 0x20 /*cheng 0629 0x24*/
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.byte 0x80, 0xf9, 0x01
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.byte 0x81, 0xb3, 0x00
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.byte 0x82, 0xff, 0x10
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@ -42,9 +45,10 @@ register_table:
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.byte 0x8e, 0xff, 0x08
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.byte 0x93, 0xff, 0x07
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.byte 0xa0, 0x00, 0x30
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.byte 0xa1, 0x00, 0x40
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.byte 0xa1, 0x00, 0x40
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.byte 0xbc, 0x03, 0x00 /* 0 non-local video memory for now. */
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.byte 0xbd, 0xfe, 0x00 /* 0 non-local video memory for now. */
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#if 0
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/* book says 0x8f, I think this is a typo */
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.byte 0xc5, 0x08, 0x00 /* hardware register, set to 0 for pci skew */
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@ -60,12 +64,12 @@ register_table:
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.byte 0xd9, 0xff, 0x03
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.byte 0xdc, 0x00, 0x10
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.byte 0xde, 0xff, 0x04
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.byte 0xf0, 0x00, 0x54
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.byte 0xf0, 0x00, 0x51 /* 0x54 cheng 0627 modify*/
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.byte 0xf1, 0x00, 0x04
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.byte 0xf2, 0x00, 0x09
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.byte 0xf3, 0x00, 0x1f
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.byte 0xf4, 0xff, 0x05
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.byte 0xf5, 0x00, 0x02
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.byte 0xf4, 0xff, 0x01 /*0x05 cheng 0627 modify*/
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.byte 0xf5, 0x00, 0x04 /*0x02 cheng 0709 modify*/
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.byte 0xf9, 0x00, 0x00
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.byte 0xfd, 0x00, 0x03
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.byte 0xfe, 0xff, 0x08
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@ -73,16 +77,18 @@ register_table:
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.byte 0x60,~0x20, 0x20
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.byte 0x02, 0x00, 0x21
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.byte 0x60,~0x20, 0x00
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.byte 0xfb, 0x00, 0x31
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.byte 0xfb, 0x00, 0x31
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.byte 0x0 /* end of table */
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m1535_table:
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.byte 0x41, 0x00, 0x0d // enable superIO recovery
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.byte 0x47, 0xff, 0x40 // enable flash rom r/w
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.byte 0x44, 0x00, 0x5d // set edge mode, primary channel IRQ 14
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.byte 0x75, 0x00, 0x0f // secondary channel IRQ 15
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.byte 0x44, 0x00, 0x1d // set edge mode, primary channel IRQ 14
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# .byte 0x75, 0x00, 0x0f // secondary channel IRQ 15
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.byte 0x58, 0x00, 0x4c // enable IDE controller
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.byte 0x70, 0x00, 0x12 // set serial IRQ data frame
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#0706cheng .byte 0x70, 0x00, 0x12 // set serial IRQ data frame
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.byte 0x72, 0x00, 0x0a /*cheng 0706 add*/
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.byte 0x0 // end of m1535_table
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chipsetinit_start:
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@ -1,342 +1,3 @@
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/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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here. The SOFTWARE has been approved for release with associated
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LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
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been authored by an employee or employees of the University of
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California, operator of the Los Alamos National Laboratory under
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Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
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U.S. Government has rights to use, reproduce, and distribute this
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SOFTWARE. The public may copy, distribute, prepare derivative works
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and publicly display this SOFTWARE without charge, provided that this
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Notice and any statement of authorship are reproduced on all copies.
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Neither the Government nor the University makes any warranty, express
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or implied, or assumes any liability or responsibility for the use of
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this SOFTWARE. If SOFTWARE is modified to produce derivative works,
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such modified SOFTWARE should be clearly marked, so as not to confuse
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it with the version available from LANL.
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*/
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/* Parts of this code Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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* Modifications by Ronnie Liu of Acer Labs Inc.
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*/
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#include <asm.h>
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#include <cpu/p5/macros.h>
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#define DOC_WIN_SEG 0xfe00
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#define DOC_STACK_SEG 0x0400
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#define SPL_RAM_SEG 0x8000
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#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
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#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
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/* wow, the usual way to to this hurts. So we do it our way:
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* 32-bit test not needed.
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*/
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/* the MCR is 32-bits. You set it, it programs SDRAM.
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* first check: get Column address size (CAS)
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* Start out assuming that it is 8 bits, then grow.
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* nicely, if we put the 32-bit MCR value in %ecs, we can
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* ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
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* set the right value.
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*/
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#define INIT_MCR $0xf663b83c
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/* GNU AS misassembles this. I can't believe what a piece of
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* trash gas has turned out to be ...
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#define LONGDELAY movw $0x1000, ax; 1: dec %ax; jnz 1b
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*/
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#define LONGDELAY 1: dec %ax; jnz 1b
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#define WDELAY outb %al, $0x80; 1: outb %al, $0x80
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#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx ; WDELAY
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/*#include <cpu/p5/start32.inc>*/
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.org 0xfe000
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.code16
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_start: jmp _realstart
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gdt: //GDT entry 0 (null segment)
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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// GDT 1
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9a, 0xcf, 0x0
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x0, 0x92, 0xcf, 0x0
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gdtptr:
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.word 4*8-1
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.long gdt /* we know the offset */
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.long 0
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_realstart:
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cli
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movw %cs, %ax
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movw %ax, %es
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.byte 0x66 /* prefix */
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.byte 0x26
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.byte 0x0f, 0x01, 0x16 /* lgdt [es:offset]*/
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.word gdtptr - EXT(_start) /* offset in segment */
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* invalidate the cache */
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invd
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data32 ljmp $0x10, $.Lprotected
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.Lprotected:
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.code32
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movw $0x18, %bx
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movw %bx, %ds
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movw %bx, %es
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/*
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movw %bx, %fs
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movw %bx, %gs
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*/
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movw %bx, %ss
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xorl %edi, %edi
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#ifdef USE_BIG_REAL
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andb $0xfe, %al
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movl %eax, %cr0
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ljmp $0xfe00, $.Lunprotected
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Lunprotected:
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code16
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#endif
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/* make the flash writeable */
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/* select the south bridge, register 44 (base) */
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/* south bridge is device 7. 7 << 3 is 0x38 */
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movl $0x80003844, %eax
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mov $0x0cf8,%dx
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outl %eax,%dx
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/* but 0x40 makes flash writeable. You need this for DoC */
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movb $0x40, %al
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/* 0xff selects register 0x47 */
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movb $0xff, %dl
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outb %al,%dx
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/* Must set regs on North Bridge (device 0) */
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movw $0x00f8,%ax /* f9h */
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movb $0xf8,%dl
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outl %eax,%dx
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movb $0xfd,%dl
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movb $0x08,%al
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outb %al,%dx
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movb $0x8c,%al /* 8eh */
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movb $0xf8,%dl
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outl %eax,%dx
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movb $0xfe,%dl
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inb %dx,%al
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orb $0x08,%al
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outb %al,%dx
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movb $0x80,%al /* 82h */
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movb $0xf8,%dl
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outl %eax,%dx
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movb $0xfe,%dl
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movb $0x10,%al
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outb %al,%dx
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// move 68 to al, we add 4 below, this is for looping
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#if 0
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movb $0x68, %al
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movl %eax, %esp
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/* CALLSP(pci_read_dword)*/
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sizeloop:
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movl %esp, %eax
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addb $4, %al
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// cmpb $0x78, %al
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// for now, just do the first bank.
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// We don't have enough bytes to figure out how to
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// handle empty banks
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cmpb $0x70, %al
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jge sizedone
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#endif
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movb $0x6c, %al
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movb $0xf8,%dl
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outl %eax,%dx
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movl %eax, %esp
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movb $0xfc, %dl
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movl INIT_MCR, %ecx
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WRITE_MCR0
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// Not only does this not work, it screws up the programming.
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#if 0
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/* check for registered. All this means is write to 0,
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* read back, if it's not the same, set 'registered',
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* read back, it it's the same you're ok.
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*/
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movb $0xa5, (%edi)
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cmpb $0xa5, (%edi)
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je nonregistered
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orb $0x40, %cl
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WRITE_MCR0
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/*
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movb $0x6c, %al
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CALLSP(pci_write_dword)
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*/
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nonregistered:
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#endif
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rorl $16, %ecx
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/* clear out the CAS, since we assume start at zero
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* and increment
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*/
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andb $0xf0, %cl
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/* test 8 bit CAS */
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Secondtry:
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movl $0x800, %esi
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movl %edi, (%edi)
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movb $3, %bl
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1:
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movb $1, (%esi) // esi is at 0x800
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cmpl %edi,(%edi)
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jnz sizeram
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inc %cl
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roll %esi
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dec %bl
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jnz 1b
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#if 0
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/* change the value we store each time. It makes debugging easier */
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movb $2, (%esi) // esi is at 0x1000
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cmpl %edi, (%edi)
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jnz sizeram
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inc %cl
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roll %esi
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movb $3, (%esi) // esi is at 0x2000
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cmpl %edi, (%edi)
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jnz sizeram
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inc %cl
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roll %esi
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movb $4, (%esi) // esi is at 0x4000
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cmpl %edi, (%edi)
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jnz sizeram
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#endif
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#if 0
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// This code does not work ...
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// OK, nothing matched.
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// This could be 64MB 2 internal banks. Dammit.
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andb $0xf0, %cl
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orb $0x0a, %cl
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WRITE_MCR0
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jmp secondtry
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#endif
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sizeram:
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rorl $16, %ecx
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/* clear the 'no multi page' bit. */
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/* NOTE: 3/22/01 -- I think this is wrong! -- rgm
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* I think we should OR IN 0x1000, which we already did!
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andw $0xefff, %cx
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*/
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WRITE_MCR0
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/*
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mov $0x6c, %al
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CALLSP(pci_write_dword)
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*/
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/* size is now in cx[19:16] */
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/* now size the dram */
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/* you had best have at least 4M; that's as small as we go */
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/* rorr 20 the ecx value, to get row size into lsb */
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movl %edi, (%edi)
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ror $20, %ecx
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/* clear the size out to 4 MB */
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andb $0xf8, %cl
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/* 4 MB */
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movl $0x400000, %esi
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1:
|
||||
#ifdef USE_BIG_REAL
|
||||
addr32 movb $4, %es:(%esi)
|
||||
#else
|
||||
/* move a 4 to the next power-of-two address.
|
||||
* if there is no memory there, it will wrap to zero
|
||||
*/
|
||||
movb $4, (%esi)
|
||||
#endif
|
||||
cmpl %edi, (%edi)
|
||||
/* if there is not a 0 at 0, the last write wrapped. Hop out */
|
||||
jne 1f
|
||||
inc %cl
|
||||
roll %esi
|
||||
jmp 1b
|
||||
/* size is now in esi */
|
||||
/* %ecx has setting for register */
|
||||
1:
|
||||
rol $20, %ecx
|
||||
/* set 4 banks. */
|
||||
orb $1, %cl
|
||||
/* COMMENT 3-22-01 RGM -- I THINK WE WANT THIS HERE TO TURN
|
||||
* MULTIBANK ON
|
||||
*/
|
||||
andb $0xef, %ch
|
||||
WRITE_MCR0
|
||||
/*
|
||||
mov $0x6c, %al
|
||||
CALLSP(pci_write_dword)
|
||||
*/
|
||||
/* bank detect */
|
||||
/* you don't need to even care how large CAS is.
|
||||
* Just set 4-bank mode, and set non-zero numbers into a few places.
|
||||
* if the byte at 0 changes, you have two banks. Trivial.
|
||||
LONGDELAY
|
||||
*/
|
||||
movl $0x1000, %esi
|
||||
movl %edi, (%edi)
|
||||
movb $5, (%esi)
|
||||
roll %esi
|
||||
movb $6, (%esi)
|
||||
roll %esi
|
||||
movb $7, (%esi)
|
||||
cmpl %edi, (%edi)
|
||||
// If @0 is unchanged, then we have four banks.
|
||||
jz 1f /* 4 banks */
|
||||
// If @0 got overwritten, then we only have two banks.
|
||||
/* clear 4 banks */
|
||||
andb $0xfe, %cl
|
||||
1:
|
||||
WRITE_MCR0
|
||||
/* Detect single/double side */
|
||||
movl %ecx, %ebx
|
||||
andl $0xe07fffff, %ecx // disable sdram
|
||||
WRITE_MCR0
|
||||
movl %ecx, %ebp
|
||||
orl $0x11800000, %ecx
|
||||
WRITE_MCR0
|
||||
movl %edi, (%edi)
|
||||
movb $0x5a, 8(%edi)
|
||||
cmpl %edi, (%edi)
|
||||
jnz 1f
|
||||
orl %ecx, %ebx // double side
|
||||
1:
|
||||
movl %ebp, %ecx
|
||||
WRITE_MCR0
|
||||
movl %ebx, %ecx
|
||||
WRITE_MCR0
|
||||
|
||||
/* jmp sizeloop
|
||||
*/
|
||||
|
||||
sizedone:
|
||||
/* Next line ASSUMES that eax contains 8000000xx */
|
||||
movb $0x7c, %al
|
||||
movb $0xf8, %dl
|
||||
outl %eax, %dx
|
||||
|
||||
movl $0x2428c411, %eax
|
||||
movb $0xfc, %dl
|
||||
outl %eax, %dx
|
||||
/* at this point, dram slot 0 is up. we hope. */
|
||||
|
||||
/* now for flash ... */
|
||||
/* NOTE: MUST NOT DESTROY %ecx! */
|
||||
/* INPUT: %al, the register. %ecx, the write data */
|
||||
/* Following code courtesy Ollie Lho: */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium
|
||||
*
|
||||
|
|
@ -367,33 +28,284 @@ sizedone:
|
|||
*
|
||||
* $Id$
|
||||
*/
|
||||
#define DOC_WIN_SEG 0xfe00
|
||||
#define DOC_STACK 0x04000
|
||||
#define SPL_RAM 0x80000
|
||||
|
||||
#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
|
||||
#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
|
||||
#include "ipl.h"
|
||||
/*
|
||||
.org 0xfe000
|
||||
*/
|
||||
.code16
|
||||
|
||||
ali_start:
|
||||
/* Must set regs on North Bridge (device 0) */
|
||||
|
||||
movw $0x00f9, %cx /*f9h*/
|
||||
movb $0x08, %al
|
||||
CALL_SP(SET_PCI)
|
||||
|
||||
movb $0x8c,%al /* 8eh */
|
||||
movb $0xf8,%dl
|
||||
outl %eax,%dx
|
||||
movb $0xfe,%dl
|
||||
inb %dx,%al
|
||||
orb $0x08,%al
|
||||
# movb $0xeb, %al
|
||||
outb %al,%dx
|
||||
|
||||
|
||||
movb $0x82, %cl /* 82h */
|
||||
movb $0x10, %al
|
||||
CALL_SP(SET_PCI)
|
||||
|
||||
movw $0x8815, %cx /*M7101 e3h*/
|
||||
movb $0x50, %al
|
||||
CALL_SP(SET_PCI)
|
||||
|
||||
movb $0x04, %cl
|
||||
movb $0x01, %al
|
||||
CALL_SP(SET_PCI) /* only for 1543c test*/
|
||||
|
||||
/* movw $0x88e0, %ax
|
||||
movb $0xf8, %dl
|
||||
outl %eax, %dx
|
||||
movb $0xff, %dl
|
||||
inb %dx, %al
|
||||
outb %al, $0x80 cheng 0615 test
|
||||
movb $0x66, %al
|
||||
outb %al, $0x80
|
||||
*/
|
||||
|
||||
/*
|
||||
movb $0xe2, %cl
|
||||
movb $0x00, %al
|
||||
CALL_SP(SET_PCI)
|
||||
*/
|
||||
|
||||
#cheng 0627 movb $0xd1, %cl /*1535d d1 reg and 1543c have not same*/
|
||||
# movb $0x46, %al
|
||||
# CALL_SP(SET_PCI)
|
||||
|
||||
movb $0xe0, %cl /*1535d f0 reg 1543c e0 reg*/
|
||||
movb $0x01, %al
|
||||
CALL_SP(SET_PCI)
|
||||
|
||||
movb $0xe2, %cl /*1535d f2 reg 1543c e2 reg*/
|
||||
movb $0x20, %al
|
||||
CALL_SP(SET_PCI)
|
||||
|
||||
/* movb $0x80, %cl
|
||||
movb $0x3e, %al
|
||||
CALL_SP(SET_PCI)
|
||||
*/
|
||||
movw $0x3847, %cx
|
||||
movb $0x40, %al
|
||||
CALL_SP(SET_PCI)
|
||||
/*--------------------------sizing loop start---------------------*/
|
||||
|
||||
movw $0xa16e, %si #cheng0607 as table before
|
||||
sizing_loop_start:
|
||||
cli # Disables the maskable
|
||||
# hardware interrupts.
|
||||
movw %cs, %ax # makes data segment ==
|
||||
movw %ax, %ds # code segment
|
||||
|
||||
movw %si, %bx
|
||||
|
||||
movb $0x02, %bl
|
||||
CALL_SP(I2C_read_byte)
|
||||
|
||||
cmpb $0x04, %al /*exist dram ?*/
|
||||
jnz sizing_end
|
||||
|
||||
addb $0x02, %bl
|
||||
CALL_SP(I2C_read_byte)
|
||||
|
||||
movb %al, %ah /*ah=column address bits*/
|
||||
subb $0x08, %ah /*convert to data sheet value*/
|
||||
|
||||
addb $0x01, %bl
|
||||
CALL_SP(I2C_read_byte)
|
||||
|
||||
shlb $0x04, %ah /*ah[7,6,5,4]=ca type*/
|
||||
movb %al, %bl /*bl=al=number of row*/
|
||||
|
||||
movb $0x0c, %al
|
||||
cmpb $0x01, %bl
|
||||
jz row_ok /*1 row*/
|
||||
movb $0x0f, %al
|
||||
# cmpb $0x02, %bl
|
||||
# jz row_ok /*2 rows*/
|
||||
# jmp sizing_end /*no rows*/
|
||||
|
||||
row_ok:
|
||||
orb %al, %ah /*ah=[ca type][number of rows]*/
|
||||
|
||||
/*get size*/
|
||||
movb $0x01f, %bl
|
||||
CALL_SP(I2C_read_byte) /*get row size*/
|
||||
|
||||
clc #convert spd value to data sheet value
|
||||
movb $0x00, %cl #chang on 0607 by cheng
|
||||
aa:
|
||||
shrb $0x01, %al
|
||||
jc size_ok
|
||||
inc %cl
|
||||
jmp aa
|
||||
|
||||
size_ok:
|
||||
movb %cl, %al /*bit: 15...12 11...........8 7......0 */
|
||||
/*ax= [ca type][number of rows][row size]*/
|
||||
movw %ax, %di /*di= [ca type][number of rows][row size]*/
|
||||
|
||||
movw %si, %cx
|
||||
xorb %ch, %ch /*cheng0606 movw $M1631, %cx */
|
||||
/*;as up mov cl, cs:[Dis_Row_Tbl][si] /cl=6eh/72h/76h */
|
||||
|
||||
movw %di, %bx
|
||||
andb $0x01, %bh
|
||||
shlb $0x03, %bh
|
||||
orb %bh, %bl /*bl= bit23-20*/
|
||||
movb %bl, %al /*al= bit23-20*/
|
||||
/*bit: 15.........12 11....4 3....0 */
|
||||
rorw $0x0c, %di /*di= [number of rows][row size][ca type]*/
|
||||
movw %di, %bx
|
||||
andb $0x0f, %bl /*bl=ca type*/
|
||||
shlb $0x04, %al
|
||||
orb %bl, %al /*al=reg:6eh/72h/76h value*/
|
||||
CALL_SP(SET_PCI)
|
||||
|
||||
inc %cl
|
||||
/*;;; ROM_CALL Get_PCI */
|
||||
/*;;; and al, 11100000b */
|
||||
/*;;; or al, 00010000b /set sdram */
|
||||
movb $0xf0, %al /*set bit[31-27]*/
|
||||
shrb $5, %bh
|
||||
orb %bh, %al
|
||||
|
||||
# outb %al, $0x80 /*-----cheng 0618-----*/
|
||||
|
||||
CALL_SP(SET_PCI)
|
||||
jmp chk_loop
|
||||
|
||||
/*if error, go here*/
|
||||
sizing_end:
|
||||
movw %si, %cx
|
||||
#cheng0606 movw $M1631, %cx
|
||||
xorb %ch, %ch
|
||||
Dis_Next_Row_Data:
|
||||
|
||||
/*;as up mov cl, cs:[Dis_Row_Tbl][si]*/
|
||||
#cheng 0615 movb $0x00, %al
|
||||
#cheng 0615 CALL_SP(SET_PCI)
|
||||
|
||||
addb $0x01, %cl
|
||||
|
||||
# movb %cl, %al /*cheng 0621*/
|
||||
# outb %al, $0x80 /*cheng 0621*/
|
||||
|
||||
movb $0xe0, %al
|
||||
CALL_SP(SET_PCI)
|
||||
|
||||
chk_loop:
|
||||
# movw %si, %ax
|
||||
# outb %al, $0x80 #cheng0608 for test
|
||||
|
||||
addw $0x0204, %si
|
||||
cmpw $0xa77a, %si
|
||||
jnz sizing_loop_start
|
||||
|
||||
# movw %si, %ax
|
||||
# outb %al, $0x80
|
||||
movb $0x7e, %cl
|
||||
movb $0x2f, %al /*cheng 0628 ago is 28h*/
|
||||
CALL_SP(SET_PCI) /*cheng 0617 refresh on */
|
||||
|
||||
jmp ipl_start
|
||||
# nop
|
||||
|
||||
/*cheng0605 start------------------------------------------------*/
|
||||
|
||||
SET_PCI:
|
||||
# movb $0x22, %al
|
||||
# outb %al, $0x80 #cheng0611
|
||||
|
||||
rorl $16, %ecx
|
||||
movw %ax, %cx
|
||||
rorl $16, %ecx
|
||||
movl $0x80000000, %eax
|
||||
movw %cx, %ax
|
||||
andb $0x0fc, %al
|
||||
|
||||
movw $0x0cf8, %dx /*index is 0cf8h*/
|
||||
outl %eax, %dx
|
||||
addb $4, %dl /*start from 0cfch*/
|
||||
movb %cl, %al
|
||||
andb $0x03, %al
|
||||
addb %al, %dl /*byte index to read*/
|
||||
rorl $16, %ecx
|
||||
movw %cx, %ax
|
||||
rorl $16, %ecx
|
||||
outb %al, %dx
|
||||
RET_SP
|
||||
|
||||
/*
|
||||
* ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium
|
||||
*
|
||||
*
|
||||
* Copyright 2000 Silicon Integrated Systems Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*
|
||||
* Reference:
|
||||
* 1. SiS 630 Specification
|
||||
* 2. System Management Bus Specification Rev 1.1
|
||||
* 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B
|
||||
* 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044
|
||||
* APR-2000, 93-SR-001-44-7L REV. 1.0
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
/*
|
||||
.code32
|
||||
*/
|
||||
ipl_start:
|
||||
#if 0
|
||||
# movb $0x55, %al
|
||||
# outb %al, $0x80 /* cheng 0617 test */
|
||||
|
||||
/*#if 0*/
|
||||
/* stack and es already set. */
|
||||
/* O.K. we have DRAM now, so set up STACK for CALL/RET */
|
||||
movw $DOC_STACK_SEG, %ax
|
||||
movw %ax, %ss
|
||||
movw $SPL_RAM_SEG, %ax
|
||||
movw %ax, %es
|
||||
movl $DOC_STACK_SEG, %esp # set %sp
|
||||
#endif
|
||||
/* movl $DOC_STACK_SEG, %esp # set %sp */
|
||||
/*#endif*/
|
||||
/* NOTE: in ollie's original code, %ds was at 0xfe00, i.e.
|
||||
* 0xfe000, i.e. base of DoC. We have to adjust for that when
|
||||
* we set %edi and %esi
|
||||
* we set %edi and %si
|
||||
*/
|
||||
movl $DOC_STACK, %esp # set %sp
|
||||
movl $SPL_RAM, %edx # start of RAM
|
||||
xorl %ecx, %ecx # clear %ecx
|
||||
movl $0xfe800, %esi # point %si to CDSN Data area
|
||||
movl $0xff000, %edi # point %di to CDSN Control area
|
||||
movl $DOC_SPL_START_BLK, %ebp # start page of LinuxBIOS
|
||||
# movl $DOC_STACK, %esp # set %sp
|
||||
# movl $SPL_RAM, %edx # start of RAM
|
||||
# xorl %ecx, %ecx # clear %ecx
|
||||
xorw %sp, %sp /*cheng 0619*/
|
||||
xorw %dx, %dx /*cheng 0619*/
|
||||
|
||||
movw $0x800, %si # point %si to CDSN Data area
|
||||
movw $0x1000, %di # point %di to CDSN Control area
|
||||
movw $DOC_SPL_START_BLK, %bp # start page of LinuxBIOS
|
||||
|
||||
movb $0x84, %al # Reset DOC Millennium
|
||||
call doc_reset
|
||||
|
|
@ -402,11 +314,11 @@ ipl_start:
|
|||
call doc_reset
|
||||
|
||||
read_next_page:
|
||||
movl $0xff000, %edi # point %di to CDSN Control area
|
||||
movw $0x1000, %di # point %di to CDSN Control area
|
||||
|
||||
flash_command:
|
||||
movb $0x03, 0x04(%edi) # start command cycle
|
||||
movb $0x00, (%esi) # issue flash command Read00
|
||||
movb $0x03, 0x04(%di) # start command cycle
|
||||
movb $0x00, (%si) # issue flash command Read00
|
||||
call doc_cycle_end
|
||||
|
||||
movw %bp, %bx # %bp is current page number
|
||||
|
|
@ -416,9 +328,9 @@ flash_address:
|
|||
movb $0x03, %cl # this one is DANGEROUS but I am
|
||||
# sure the upper 3 bytes == 0x00
|
||||
|
||||
movb $0x05, 0x04(%edi) # start address cycle
|
||||
movb $0x05, 0x04(%di) # start address cycle
|
||||
0:
|
||||
movb %bl, (%esi) # write address to CDSNIO
|
||||
movb %bl, (%si) # write address to CDSNIO
|
||||
shrw $0x08, %bx # shift next address byte
|
||||
loop 0b
|
||||
|
||||
|
|
@ -430,21 +342,28 @@ wait_for_flash_ready:
|
|||
doc_delay:
|
||||
movb $0x04, %cl # this one is DANGEROUS but I am
|
||||
# sure the upper 3 bytes == 0x00
|
||||
# movb $0x33, %al
|
||||
# outb %al, $0x80 /*0618 test*/
|
||||
|
||||
0:
|
||||
movb 0x20(%edi), %al # read DOC NOP retisger
|
||||
movb 0x20(%di), %al # read DOC NOP retisger
|
||||
loop 0b # four times
|
||||
# outb %al, $0x80 /*0618 test*/
|
||||
|
||||
testb $0x80, 0x04(%edi) # is flash ready ?
|
||||
testb $0x80, 0x04(%di) # is flash ready ?
|
||||
jz wait_for_flash_ready
|
||||
|
||||
movb 0x1d(%edi), %al # init read pipeline
|
||||
# movb $0x33, %al
|
||||
# outb %al, $0x80 /*---cheng 0618 test---*/
|
||||
|
||||
movb 0x1d(%di), %al # init read pipeline
|
||||
movw $0x100, %cx # 1 page = 512 bytes
|
||||
movl $0xfe800, %esi # point %si to CDSN Data area
|
||||
movl %edx, %edi # restore saved current destination
|
||||
movw $0x800, %si # point %si to CDSN Data area
|
||||
movw %dx, %di # restore saved current destination
|
||||
rep
|
||||
movsw
|
||||
|
||||
movl %edi, %edx # save current destination
|
||||
movw %di, %dx # save current destination
|
||||
incw %bp # increse current page number
|
||||
cmpw $128, %bp # moved 63 KB ??
|
||||
jl read_next_page # no, read next page
|
||||
|
|
@ -453,56 +372,133 @@ sis630ipl_end:
|
|||
# jmp to 8000:0000, where SPL
|
||||
# (LinuxBIOS) starts in RAM
|
||||
# ljmp $0x10,$0x8000
|
||||
jmp spl_vector
|
||||
|
||||
# movb $0x66, %al
|
||||
# outb %al, $0x80 /*0618 test*/
|
||||
|
||||
jmp spl_vector
|
||||
|
||||
/* ------------------------------------------------------------------------------------------*/
|
||||
doc_reset:
|
||||
/* Input: AL = value write to DOC_CONTROL register
|
||||
Clobberd: CX */
|
||||
movb %al, 0x02(%edi) # write DoC Control retister
|
||||
movb %al, 0x02(%edi) # twice
|
||||
movb %al, 0x02(%di) # write DoC Control retister
|
||||
movb %al, 0x02(%di) # twice
|
||||
ret # End of doc_reset
|
||||
|
||||
doc_cycle_end:
|
||||
movb $0x00, 0x1e(%edi) # flush write pepeline
|
||||
movb $0x01, 0x04(%edi) # end command cycle
|
||||
movb $0x00, 0x1e(%di) # flush write pepeline
|
||||
movb $0x01, 0x04(%di) # end command cycle
|
||||
ret
|
||||
|
||||
|
||||
/*---------------------------------------table--------------------*/
|
||||
/* dimm 0 1 2 */
|
||||
/*
|
||||
dimm_tbl:
|
||||
.byte 0x0a1, 0x0a3, 0x0a5
|
||||
size_tbl:
|
||||
.byte 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
|
||||
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
|
||||
Dis_Row_Tbl:
|
||||
.byte 0x06e, 0x072, 0x076
|
||||
*/
|
||||
/*
|
||||
;=============================================
|
||||
; =
|
||||
; Read SPD value for Dram sizing = CHENG 3.7.2001
|
||||
; =
|
||||
; INPUT bl := offset to read =
|
||||
; bh := eeprom ID =
|
||||
; =
|
||||
; OUTPUT al := data =
|
||||
; carry clear = read successful =
|
||||
; carry set = read failed =
|
||||
; =
|
||||
; CHANGES REGISTERS: cx, dx, al =
|
||||
; =
|
||||
;=============================================
|
||||
*/
|
||||
I2C_read_byte:
|
||||
movw $0x5000, %dx
|
||||
movb $0x0ff, %al
|
||||
outb %al, %dx #clear status
|
||||
# movb $0x77, %al /*cheng 0615 test */
|
||||
# outb %al, $0x80
|
||||
|
||||
/* we don't need these. We only do I/O to MCR 0 */
|
||||
#if 0
|
||||
pci_write_dword:
|
||||
mov $0,%ah
|
||||
mov $0x80000000,%edx
|
||||
or %ax,%dx
|
||||
mov %edx,%eax
|
||||
mov $0x0cf8,%dx
|
||||
outl %eax,%dx
|
||||
mov $0x0fc,%dl
|
||||
mov %ecx, %eax
|
||||
outl %eax,%dx
|
||||
RETSP
|
||||
pci_read_dword:
|
||||
mov $0,%ah
|
||||
mov $0x80000000,%edx
|
||||
or %ax,%dx
|
||||
mov %edx,%eax
|
||||
mov $0x0cf8,%dx
|
||||
outl %eax,%dx
|
||||
mov $0x0fc,%dl
|
||||
inl %dx, %eax
|
||||
mov %eax, %ecx
|
||||
RETSP
|
||||
#endif
|
||||
1:
|
||||
inb %dx, %al
|
||||
# nop
|
||||
# jmp c0
|
||||
#c0:
|
||||
testb $0x04, %al
|
||||
jz 1b #wait till idle
|
||||
|
||||
movb $0x03, %dl
|
||||
movb %bh, %al
|
||||
outb %al, %dx #spd address
|
||||
# nop
|
||||
# jmp c1
|
||||
#c1:
|
||||
movb $0x01, %dl
|
||||
movb $0x20, %al
|
||||
outb %al, %dx #set read/write byte command
|
||||
# nop
|
||||
# jmp c2
|
||||
#c2:
|
||||
movb $0x07, %dl
|
||||
movb %bl, %al
|
||||
outb %al, %dx #set the offset of register
|
||||
# nop
|
||||
# jmp c3
|
||||
#c3:
|
||||
movb $0x02, %dl
|
||||
movb $0x0ff, %al
|
||||
outb %al, %dx #start command
|
||||
# nop
|
||||
# jmp c4
|
||||
#c4:
|
||||
/*;wait for command complete*/
|
||||
movw $0x100, %cx #loop count
|
||||
movb $0x00, %dl
|
||||
chk_status_final:
|
||||
inb %dx, %al
|
||||
# nop
|
||||
# jmp c5
|
||||
#c5:
|
||||
testb $0x10, %al
|
||||
jnz send_ok
|
||||
loop chk_status_final
|
||||
/*;read failed*/
|
||||
#cheng0606 stc
|
||||
jmp spd_end
|
||||
send_ok:
|
||||
movb $0x04, %dl
|
||||
inb %dx, %al
|
||||
# nop
|
||||
# jmp c6
|
||||
#c6:
|
||||
#cheng0606 clc
|
||||
spd_end:
|
||||
RET_SP
|
||||
|
||||
/*cheng0605 end-----------------------------------------------*/
|
||||
|
||||
.org 0x01f0
|
||||
|
||||
.org 0xfe1f0
|
||||
reset_vector:
|
||||
.byte 0xea # jmp to fe00:0000, where IPL
|
||||
.word 0x0000, DOC_WIN_SEG # starts in DoC
|
||||
.code32
|
||||
#.code32
|
||||
spl_vector:
|
||||
invd
|
||||
jmpl $0x10, $0x80000
|
||||
# movb $0x55, %al
|
||||
# outb %al, $0x80 /* cheng 0617 test */
|
||||
|
||||
.byte 0xea
|
||||
.word 0x0000, 0x8000
|
||||
|
||||
# invd
|
||||
# jmpl $0x10, $0x80000
|
||||
# jmpl $0x80000
|
||||
# put this here to buy some room!
|
||||
pad: .byte 0,0
|
||||
|
||||
pad: .byte 0,0,0,0,0,0
|
||||
|
|
|
|||
17
src/northbridge/acer/m1631/ipl.h
Normal file
17
src/northbridge/acer/m1631/ipl.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
#define DOC_WIN_SEG 0xfe00
|
||||
#define DOC_STACK_SEG 0x0400
|
||||
#define SPL_RAM_SEG 0x8000
|
||||
|
||||
#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
|
||||
#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
|
||||
|
||||
|
||||
#define DOC_STACK 0x04000
|
||||
#define SPL_RAM 0x80000
|
||||
|
||||
|
||||
#define CALL_SP(func) lea 0f, %sp ; jmp func ; 0:
|
||||
|
||||
#define RET_SP jmp *%sp
|
||||
|
||||
|
||||
|
|
@ -34,6 +34,7 @@ unsigned long sizeram()
|
|||
|
||||
u32 ram;
|
||||
unsigned long size;
|
||||
unsigned long sizeall=0;
|
||||
pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
|
||||
|
||||
if (! pcidev)
|
||||
|
|
@ -45,17 +46,24 @@ unsigned long sizeram()
|
|||
|
||||
pci_read_config_dword(pcidev, i, &ram);
|
||||
size = (1 << (((ram >> 20) & 0x7))) * (0x400000);
|
||||
if ((ram & 0x6000000) == 0x00000000)
|
||||
size=0;
|
||||
printk("0x%x 0x%x, size 0x%x\n", i, ram, size);
|
||||
}
|
||||
pci_read_config_dword(pcidev, 0x6c, &ram);
|
||||
|
||||
for(i = 0x6c; i < 0x78; i +=4)
|
||||
{
|
||||
pci_read_config_dword(pcidev, i, &ram);
|
||||
size = (1 << (((ram >> 20) & 0x7))) * (0x400000);
|
||||
if ((ram & 0x1800000) == 0x1800000)
|
||||
size <<= 1;
|
||||
printk("size in 0x6c is 0x%x\n", size);
|
||||
#if 1
|
||||
printk("NOT SIZING OTHER TWO SLOTS. ONLY ONE SLOT RIGHT NOW\n");
|
||||
return size/1024;
|
||||
#endif
|
||||
if ((ram & 0x6000000) == 0x00000000)
|
||||
size=0;
|
||||
|
||||
printk("size in 0x%x is 0x%x\n", i, size);
|
||||
sizeall=sizeall+size;
|
||||
}
|
||||
return sizeall/1024;
|
||||
cp = (unsigned char *) size;
|
||||
// now do the other two banks.
|
||||
#define INIT_MCR 0xf663b83c
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue