Initial AMD Barcelona support for rev Bx.
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
parent
2006b38fed
commit
8ae8c88220
90 changed files with 27619 additions and 33 deletions
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@ -1,6 +1,6 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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*
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* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -15,23 +15,30 @@
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#define CacheSize DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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/* leave some space for global variable to pass to RAM stage */
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#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
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#if CAR_FAM10 == 1
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#define CacheSizeAPStack 0x400 /* 1K */
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#endif
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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/* Save the BIST result */
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movl %eax, %ebp
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/* for normal part %ebx already contain cpu_init_detected from fallback call */
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/*for normal part %ebx already contain cpu_init_detected from fallback call */
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cache_as_ram_setup:
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movb $0xA0, %al
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outb %al, $0x80
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/* hope we can skip the double set for normal part */
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#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
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@ -42,6 +49,53 @@ cache_as_ram_setup:
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andl $(1 << 11), %eax
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movl %eax, %ebx /* We store the status */
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#if CAR_FAM10 == 1
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/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
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/* Only BSP needed, for other nodes set during HT/memory init. */
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/* So we need to check if it is BSP */
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movl $0x1b, %ecx
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rdmsr
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bt $8, %eax /*BSC */
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jnc CAR_FAM10_out
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/* Enable RT tables on BSP */
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movl $0x8000c06c, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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addw $4, %dx
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inl %dx, %eax
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btr $0, %eax
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outl %eax, %dx
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/* Setup temporary DRAM map: [0,16M) bit 0-23 */
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movl $0x8000c144, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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addw $4, %dx
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movl $0, %eax
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outl %eax, %dx
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movl $0x8000c140, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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addw $4, %dx
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movl $3, %eax
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outl %eax, %dx
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CAR_FAM10_out:
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#endif
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#if CAR_FAM10 == 1
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/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
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Re-enable it in after RAM is initialized and before CAR is disabled */
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movl $0xc001102a, %ecx
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rdmsr
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bts $15, %eax
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wrmsr
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#endif
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/* Set MtrrFixDramModEn for clear fixed mtrr */
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enable_fixed_mtrr_dram_modify:
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movl $SYSCFG_MSR, %ecx
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@ -53,7 +107,7 @@ enable_fixed_mtrr_dram_modify:
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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@ -68,9 +122,14 @@ clear_fixed_var_mtrr_out:
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#if CacheSize == 0x10000
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/* enable caching for 64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000 */
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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movl $0x268, %ecx /* fix4k_c0000*/
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#if CAR_FAM10 == 1
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movl $0x1e1e1e1e, %edx /* WB MEM type */
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#else
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movl $0x06060606, %edx /* WB IO type */
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#endif
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movl %edx, %eax
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wrmsr
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movl $0x269, %ecx
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wrmsr
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@ -78,38 +137,62 @@ clear_fixed_var_mtrr_out:
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#if CacheSize == 0xc000
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/* enable caching for 16K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c4000 */
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movl $0x06060606, %edx /* WB IO type */
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movl $0x268, %ecx /* fix4k_c4000*/
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#if CAR_FAM10 == 1
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movl $0x1e1e1e1e, %edx /* WB MEM type */
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#else
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movl $0x06060606, %edx /* WB IO type */
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#endif
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xorl %eax, %eax
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wrmsr
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000 */
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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movl $0x269, %ecx /* fix4k_c8000*/
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#if CAR_FAM10 == 1
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movl $0x1e1e1e1e, %edx /* WB MEM type */
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#else
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movl $0x06060606, %edx /* WB IO type */
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#endif
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movl %edx, %eax
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wrmsr
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#endif
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#if CacheSize == 0x8000
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000 */
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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movl $0x269, %ecx /* fix4k_c8000*/
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#if CAR_FAM10 == 1
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movl $0x1e1e1e1e, %edx /* WB MEM type */
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#else
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movl $0x06060606, %edx /* WB IO type */
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#endif
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movl %edx, %eax
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wrmsr
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#endif
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#if CacheSize < 0x8000
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/* enable caching for 16K/8K/4K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_cc000*/
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#if CacheSize == 0x4000
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#if CacheSize == 0x4000
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#if CAR_FAM10 == 1
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movl $0x1e1e1e1e, %edx /* WB MEM type */
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#else
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movl $0x06060606, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x2000
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#endif
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#endif
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#if CacheSize == 0x2000
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#if CAR_FAM10 == 1
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movl $0x1e1e0000, %edx /* WB MEM type */
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#else
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movl $0x06060000, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x1000
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#endif
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#endif
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#if CacheSize == 0x1000
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#if CAR_FAM10 == 1
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movl $0x1e000000, %edx /* WB MEM type */
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#else
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movl $0x06000000, %edx /* WB IO type */
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#endif
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#endif
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#endif
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xorl %eax, %eax
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wrmsr
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#endif
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@ -160,13 +243,27 @@ clear_fixed_var_mtrr_out:
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wrmsr
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#endif
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movb $0xA1, %al
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outb %al, $0x80
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
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#if CAR_FAM10 == 1
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/* So we need to check if it is BSP */
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movl $0x1b, %ecx
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rdmsr
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bt $8, %eax /*BSC */
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jnc CAR_FAM10_ap
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#endif
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movb $0xA2, %al
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outb %al, $0x80
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#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
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/* Read the range with lodsl*/
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cld
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movl $CacheBase, %esi
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/* set up the stack pointer */
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movl $(CacheBase + CacheSize - GlobalVarSize), %eax
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movl %eax, %esp
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movb $0xA3, %al
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outb %al, $0x80
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#if CAR_FAM10 == 1
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jmp CAR_FAM10_ap_out
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CAR_FAM10_ap:
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/* need to set stack pointer for AP */
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/* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
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/* So need to get the NodeID and CoreID at first */
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/* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
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/* store our init detected */
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movl %ebx, %esi
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/* get the coreid bits at first */
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movl $0x80000008, %eax
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cpuid
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shrl $12, %ecx
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andl $0x0f, %ecx
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movl %ecx, %edi
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/* get the initial apic id */
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movl $1, %eax
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cpuid
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shrl $24, %ebx
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/* get the nb cfg bit 54 */
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movl $0xc001001f, %ecx /* NB_CFG_MSR */
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rdmsr
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movl %edi, %ecx /* CoreID bits */
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bt $(54-32), %edx
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jc roll_cfg
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rolb %cl, %bl
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roll_cfg:
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/* calculate stack pointer */
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movl $CacheSizeAPStack, %eax
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mull %ebx
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movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
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subl %eax, %esp
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/* retrive init detected */
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movl %esi, %ebx
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movb $0xA4, %al
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outb %al, $0x80
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CAR_FAM10_ap_out:
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#endif
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movb $0xA5, %al
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outb %al, $0x80
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %ebx /* init detected */
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call cache_as_ram_main
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/* We will not go back */
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movb $0xAF, %al /* Should never see this postcode */
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outb %al, $0x80
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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