From 8a7abb9b5e82f23be6e96608f5c7c98852ee5220 Mon Sep 17 00:00:00 2001
From: Li-Ta Lo <ollie@lanl.gov>
Date: Mon, 27 Nov 2000 06:37:33 +0000
Subject: [PATCH] moving DLL stuff out from ipl.S

---
 src/mainboard/leadtek/winfast6300/mainboard.c |  2 +-
 src/northsouthbridge/sis/630/ipl.S            | 19 ++-----------------
 src/northsouthbridge/sis/630/ipl.h            |  2 +-
 src/northsouthbridge/sis/630/southbridge.c    |  7 +++++--
 4 files changed, 9 insertions(+), 21 deletions(-)

diff --git a/src/mainboard/leadtek/winfast6300/mainboard.c b/src/mainboard/leadtek/winfast6300/mainboard.c
index 7e27fd8753..d513e6420c 100644
--- a/src/mainboard/leadtek/winfast6300/mainboard.c
+++ b/src/mainboard/leadtek/winfast6300/mainboard.c
@@ -15,6 +15,6 @@ final_mainboard_fixup(void)
     final_superio_fixup();
 
     printk(KERN_INFO 
-	"Final mainboard fixup done for Winfast 6300 (and similar)\n");
+	   "Final mainboard fixup done for Winfast 6300 (and similar)\n");
 
 }
diff --git a/src/northsouthbridge/sis/630/ipl.S b/src/northsouthbridge/sis/630/ipl.S
index f857e99327..db84600e54 100644
--- a/src/northsouthbridge/sis/630/ipl.S
+++ b/src/northsouthbridge/sis/630/ipl.S
@@ -365,29 +365,14 @@ sdram_type_bank_2:
 
 pci_init_table:
 #		Reg.	Value	times
-#	.byte	0x55,	0x01	#0x01
-#	.byte	0x04,	0x05	#0x01
 
-#ifndef SIS630S
-	.byte	0x8c,	0x66	# set Clock DLL control register
-	.byte	0x8d,	0x66	# 0x8c ~ 0x8f,
-	.byte	0x8e,	0x03	# these values are very M/B
-	.byte	0x8f,	0x55	# specific
-#else /* SIS630S */
-	.byte	0x8c,	0x27	# set Clock DLL control register
-	.byte	0x8d,	0x77	# 0x8c ~ 0x8f,
-	.byte	0x8e,	0x01	# these values are very M/B
-	.byte	0x8f,	0x07	# specific
-#endif /* SIS630S */
-	
+#include "dll.inc"
+
 	.byte	0x57,	0x80	#0x01
 	.byte	0x57,	0x40	#0x01
 	.byte	0x57,	0x20	#0x06
 	.byte	0x57,	0x20	#0x06
 	.byte	0x57,	0x20	#0x06
-#	.byte	0x57,	0x20	#0x06
-#	.byte	0x57,	0x20	#0x06
-#	.byte	0x57,	0x20	#0x06
 	.byte	0x52,	0x01	#0x01
 	.byte	0x00 /* Null, End of table */
 
diff --git a/src/northsouthbridge/sis/630/ipl.h b/src/northsouthbridge/sis/630/ipl.h
index 3361e9a373..8b364da493 100644
--- a/src/northsouthbridge/sis/630/ipl.h
+++ b/src/northsouthbridge/sis/630/ipl.h
@@ -11,7 +11,7 @@
 #define SPL_RAM_SEG		0x8000
 
 #define DOC_SPL_START_BLK	2	/* 0,1 for IPL */
-#define DOC_SPL_SIZE_IN_PAGE	126     /* 1 page = 512 bytes, 256k */
+#define DOC_SPL_SIZE_IN_PAGE	126     /* 1 page = 512 bytes, total 63kB */
 
 #define RET_LABEL(label)	\
 	jmp label##_done
diff --git a/src/northsouthbridge/sis/630/southbridge.c b/src/northsouthbridge/sis/630/southbridge.c
index 9dc2a08c7a..b682714f2e 100644
--- a/src/northsouthbridge/sis/630/southbridge.c
+++ b/src/northsouthbridge/sis/630/southbridge.c
@@ -43,8 +43,9 @@ void nvram_on()
 	/* turn on sis630 nvram. */
 	pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, (void *)NULL);
 	if (pcidev != NULL) {
-		/* Enable FFF80000 to FFFFFFFF decode */
-		pci_write_config_byte(pcidev, 0x40, 0x03);
+		/* Enable FFF80000 to FFFFFFFF decode. You have to also enable
+		   PCI Posted write for devices on sourthbridge */
+		pci_write_config_byte(pcidev, 0x40, 0x33);
 		/* Flash can be flashed */
 		pci_write_config_byte(pcidev, 0x45, 0x40);
 		printk(KERN_INFO "Enabled in SIS 503 regs 0x40 and 0x45\n");
@@ -75,6 +76,7 @@ final_southbridge_fixup()
 {
 	struct pci_dev *pcidev;
 
+#ifdef OLD_KERNEL_HACK
 	// ethernet fixup. This should all work, and doesn't, yet. 
 	// so we hack it for now. 
 	// need a manifest constant for the enet device. 
@@ -168,6 +170,7 @@ final_southbridge_fixup()
 	} else {
 		printk(KERN_EMERG "Can't find south bridge!\n");
 	}
+#endif /* OLD_KERNEL_HACK */
 
 	printk(KERN_INFO "Southbridge fixup done for SIS 503\n");
 }