diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c
index 628af99112..4de941fa61 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_v2.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c
@@ -282,7 +282,7 @@ void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp)
 		    DP_TX2_PRE_EMPH_MASK | DP_TX3_PRE_EMPH_MASK);
 }
 
-void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp)
+static void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp)
 {
 	u32 mask = RGS_BG_CORE_EN_READY_MASK | RGS_AUX_LDO_EN_READY_MASK;
 
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
index 7f49e5608b..1727b84eb6 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
@@ -21,7 +21,6 @@ extern const int dptx_hal_driving_offset_size;
 
 void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp);
 void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
-void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp);
 void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
 void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);