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soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx

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Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.

TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.

Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-06-09 21:57:49 +05:30
commit 8a18bd8500
5 changed files with 67 additions and 58 deletions
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5
src/mainboard/intel/adlrvp/devicetree.cb
View file

@ -125,8 +125,9 @@ chip soc/intel/alderlake
# Enable EDP in PortA
register "DdiPortAConfig" = "1"
# Enable HDMI in Port B
register "DdiPortBDdc" = "1"
register "DdiPortBHpd" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
# TCSS USB3
register "TcssAuxOri" = "0"

5
src/mainboard/intel/adlrvp/devicetree_m.cb
View file

@ -82,8 +82,9 @@ chip soc/intel/alderlake
# Enable EDP in PortA
register "DdiPortAConfig" = "1"
# Enable HDMI in Port B
register "DdiPortBDdc" = "1"
register "DdiPortBHpd" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
# TCSS USB3
register "TcssAuxOri" = "0"

22
src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
View file

@ -118,21 +118,13 @@ chip soc/intel/alderlake
register "DdiPortAConfig" = "1" # eDP
register "DdiPortBConfig" = "0"
register "DdiPortAHpd" = "1"
register "DdiPortBHpd" = "1"
register "DdiPortCHpd" = "0"
register "DdiPort1Hpd" = "1"
register "DdiPort2Hpd" = "1"
register "DdiPort3Hpd" = "0"
register "DdiPort4Hpd" = "0"
register "DdiPortADdc" = "0"
register "DdiPortBDdc" = "1"
register "DdiPortCDdc" = "0"
register "DdiPort1Ddc" = "0"
register "DdiPort2Ddc" = "0"
register "DdiPort3Ddc" = "0"
register "DdiPort4Ddc" = "0"
# Enable Display Port Configuration
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_1] = DDI_ENABLE_HPD,
[DDI_PORT_2] = DDI_ENABLE_HPD,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+