From 88ce01a4d5862c5cd286a1ef5f9e65882e5a8041 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Philipp=20Gro=C3=9F?= Date: Fri, 4 Oct 2024 15:03:49 +0200 Subject: [PATCH] mb/asrock: Add Z87 Extreme4 (Haswell) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This port was done via autoport and subsequent manual tweaking. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Special thanks to Angel for enabling various LEDs/PCD functions! Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - HDMI-Out Port - DVI-D Port - RJ-45 Gigabit LAN Port - Both USB 2.0 Ports - All four USB 3.1 Gen1 Ports - All three USB 2.0 headers - Both USB 3.1 Gen1 headers - Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH) - All six SATA3 6.0 Gb/s connectors by Intel - All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) working: - both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 (fix will soon be merged) not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Signed-off-by: Jan Philipp Groß Reviewed-on: https://review.coreboot.org/c/coreboot/+/84672 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asrock/z87_extreme4/Kconfig | 28 +++ .../asrock/z87_extreme4/Kconfig.name | 4 + src/mainboard/asrock/z87_extreme4/Makefile.mk | 6 + src/mainboard/asrock/z87_extreme4/acpi/ec.asl | 3 + .../asrock/z87_extreme4/acpi/platform.asl | 10 + .../asrock/z87_extreme4/acpi/superio.asl | 3 + .../asrock/z87_extreme4/board_info.txt | 7 + src/mainboard/asrock/z87_extreme4/bootblock.c | 47 +++++ src/mainboard/asrock/z87_extreme4/data.vbt | Bin 0 -> 4399 bytes .../asrock/z87_extreme4/devicetree.cb | 143 +++++++++++++ src/mainboard/asrock/z87_extreme4/dsdt.asl | 27 +++ .../asrock/z87_extreme4/gma-mainboard.ads | 19 ++ src/mainboard/asrock/z87_extreme4/gpio.c | 191 ++++++++++++++++++ src/mainboard/asrock/z87_extreme4/hda_verb.c | 24 +++ src/mainboard/asrock/z87_extreme4/mainboard.c | 46 +++++ src/mainboard/asrock/z87_extreme4/romstage.c | 37 ++++ .../asrock/z87_extreme4/smihandler.c | 45 +++++ 17 files changed, 640 insertions(+) create mode 100644 src/mainboard/asrock/z87_extreme4/Kconfig create mode 100644 src/mainboard/asrock/z87_extreme4/Kconfig.name create mode 100644 src/mainboard/asrock/z87_extreme4/Makefile.mk create mode 100644 src/mainboard/asrock/z87_extreme4/acpi/ec.asl create mode 100644 src/mainboard/asrock/z87_extreme4/acpi/platform.asl create mode 100644 src/mainboard/asrock/z87_extreme4/acpi/superio.asl create mode 100644 src/mainboard/asrock/z87_extreme4/board_info.txt create mode 100644 src/mainboard/asrock/z87_extreme4/bootblock.c create mode 100644 src/mainboard/asrock/z87_extreme4/data.vbt create mode 100644 src/mainboard/asrock/z87_extreme4/devicetree.cb create mode 100644 src/mainboard/asrock/z87_extreme4/dsdt.asl create mode 100644 src/mainboard/asrock/z87_extreme4/gma-mainboard.ads create mode 100644 src/mainboard/asrock/z87_extreme4/gpio.c create mode 100644 src/mainboard/asrock/z87_extreme4/hda_verb.c create mode 100644 src/mainboard/asrock/z87_extreme4/mainboard.c create mode 100644 src/mainboard/asrock/z87_extreme4/romstage.c create mode 100644 src/mainboard/asrock/z87_extreme4/smihandler.c diff --git a/src/mainboard/asrock/z87_extreme4/Kconfig b/src/mainboard/asrock/z87_extreme4/Kconfig new file mode 100644 index 0000000000..3ef4afad0c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_EXTREME4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_extreme4" + +config MAINBOARD_PART_NUMBER + default "Z87 Extreme4" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB3_23 (Upper) + # Header: USB2_3 +endif diff --git a/src/mainboard/asrock/z87_extreme4/Kconfig.name b/src/mainboard/asrock/z87_extreme4/Kconfig.name new file mode 100644 index 0000000000..65c3e2f23f --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_EXTREME4 + bool "Z87 Extreme4" diff --git a/src/mainboard/asrock/z87_extreme4/Makefile.mk b/src/mainboard/asrock/z87_extreme4/Makefile.mk new file mode 100644 index 0000000000..c3cf55d397 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_extreme4/acpi/ec.asl b/src/mainboard/asrock/z87_extreme4/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme4/acpi/platform.asl b/src/mainboard/asrock/z87_extreme4/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_extreme4/acpi/superio.asl b/src/mainboard/asrock/z87_extreme4/acpi/superio.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme4/board_info.txt b/src/mainboard/asrock/z87_extreme4/board_info.txt new file mode 100644 index 0000000000..a9a7e67598 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Extreme4/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_extreme4/bootblock.c b/src/mainboard/asrock/z87_extreme4/bootblock.c new file mode 100644 index 0000000000..3d3da8e5e7 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/bootblock.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define GPIO1_ENABLE_DEV PNP_DEV(0x2e, NCT6776_GPIO1234567_V) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x48); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power on the status LEDs */ + pnp_set_logical_device(GPIO1_ENABLE_DEV); + pnp_unset_and_set_config(GPIO1_ENABLE_DEV, 0x30, 0, 1 << 1); + + pnp_set_logical_device(GPIO1_DEV); + pnp_write_config(GPIO1_DEV, 0xf0, 0x30); + pnp_write_config(GPIO1_DEV, 0xf1, 0x31); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_extreme4/data.vbt b/src/mainboard/asrock/z87_extreme4/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..e973accf06c36860dfc8741a7292cab6e8c03df0 GIT binary patch literal 4399 zcmdT`U2GIp6h3!mc6WAmX1X0JY*(nK(7?9Rc3Mbnni^-@E$)_uZht71U|3*RL<^Jx z27eM(tPy{r8$$>f0!=VRNF;qRy!e2|1QG~ABSc@6CqsBJJP>0Hu%0_JyC4xR3AFdiLT*^^A7D;Y4Mxw4C{)1@oXH@GGi9g42$O7?Xx#iKA2 z3c;IK05XitR9jox+7g?$XGbFg^%x&qiOaUE+c=tSj%ByKxP8kQrn(atUB5m%njK%e zJ)6P7;isd>IW?tg$HvhNF5j_fU3R2j))0ARAy0?tIJic+m^V>1f zU5~A%X*LpP3))S_?k(eEO&A>=#Q`3(4F|H@vg0phGfkSpIZlEsF#zU)3I>ebXa&E_ zR9TA4RzyY*lcLP3Wf+qzjY&OB%1Bm%S@jH)l2s?+LJ5N)XiSg*YKtu*jokJFh+GS% za}N@Hn}%S}8>!+B{DuK|cz_2Ok_}+NMLVFw4#-`Qf!-nUAwz*1=rSZ-2IBXg7;_lx zZ}A{kuxQ*(Kd1na`XbE+vvqM>dq=0$6&JZpTej<2x!1aQV1D~DD z9CLN0qai54`}L4J==u-3e*aZ__&{-Wz}0sfkvsi`g3kvx3+F;mD9BIp7FfhUsbVpg zDemf|twk~A-Vc%H`5kfZ3k83gZd>X1;I7IUC@srEfj(r*!)gUiL2ZtD;I1p=onfA_ zIb4?{N7n5Df@l2R0i`#K#+?jBe@XxI0CfiRQXvuL&WYJJ?FxXxTbc+vLDBudbnhy7 z!P^KG?}EQHfTi#MYlh!0c4gC5QuTAiP>aRFc2pe#Z`gU{>nz6HssGC-Gndj-5$)O_ zyHyUroX`Q1OHyl6Yd2>{m#^KFE%Rnp95U5lMPa@f+SBIrGh{Zv{(dkmb8Lp=srj^d z=cWGed~0NX(G!2lGS^MDTGq*;ClrCUU80jrwQZLN>|KQ{mbYgySzc$$QL7_R4ZqW` z8uARm`JJXM%K0s1x2!N{dGsutrviN5ca80t@&B}(M3r+b6lS-%Rk@~;pFsXBkF6#ufzd%i z27yiq5~!5@7{noZTOd7SbohvpTXsWiSDYf#PzMnjJBu?gdMcBNL>M7DM5qvMBl-(7 z5~2@poA%%sN&Q|B&nx(=V#oo-2w;1_=nW`C0emH3ycbaR1@Mc2aW0^IAHbUdBd982 z6)n{mP?gmx?pBSxs&YuhuT|rss$5dhs~I6pnX6%3GgfIzM#FbBPmx-DcxA7E2BDos2d;a%5fdP(~X~X<*KeVT$OUdC6=qC#YR(F9#?5fjtHu) zudyI$PsIY-Pp6M1tpaytpg1DjpJB2Bp=D$?Msih7hHBb&36w7ql~OI6s{FK73R^dA@&Qu9-S8tHdBefZM9&Er-Eu zuui8ZGG?gXIeGFnh%_BJ!{3~fHiPCcc(9CKTnWQu3TK(B+0Eaw^C0GFJ=&RUx97vX z*QU^s3vF$0v_=|ljfDsmHUpI~@BPEnq uE`X6^y{GBK|3I#VJ7nP_@b(f)W`a)qD + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/z87_extreme4/gma-mainboard.ads b/src/mainboard/asrock/z87_extreme4/gma-mainboard.ads new file mode 100644 index 0000000000..c0b52b2e2d --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- DP + HDMI1, -- DVI-D + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- D-SUB + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_extreme4/gpio.c b/src/mainboard/asrock/z87_extreme4/gpio.c new file mode 100644 index 0000000000..bca2aac165 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_extreme4/hda_verb.c b/src/mainboard/asrock/z87_extreme4/hda_verb.c new file mode 100644 index 0000000000..ab7da869de --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_extreme4/mainboard.c b/src/mainboard/asrock/z87_extreme4/mainboard.c new file mode 100644 index 0000000000..1e62d65d2e --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/mainboard.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ +#include +#include +#include +#include +#include +#include +#include + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void turn_off_leds(void *unused) +{ + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + pnp_write_config(GPIO1_DEV, 0x27, 0xd0); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, turn_off_leds, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, turn_off_leds, NULL); diff --git a/src/mainboard/asrock/z87_extreme4/romstage.c b/src/mainboard/asrock/z87_extreme4/romstage.c new file mode 100644 index 0000000000..d52bc820ba --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asrock/z87_extreme4/smihandler.c b/src/mainboard/asrock/z87_extreme4/smihandler.c new file mode 100644 index 0000000000..d6ebcef9a0 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme4/smihandler.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* + * Cut off power to LEDs when system goes to sleep. + */ + if (slp_typ >= ACPI_S3) { + + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); + } +}