From 883103c77f16a070a7d92ee20a4089edf8d16e48 Mon Sep 17 00:00:00 2001 From: Avi Uday Date: Mon, 25 Aug 2025 19:25:45 +0530 Subject: [PATCH] mb/google/ocelot: Disable memory training progress bar Set disable_progress_bar to disable the memory progress bar for ocelot board as this is an OEM feature and might not be used by all. TEST=Verify that ocelot builds without any error Change-Id: Ifef7a2645dce696f32cea42fd928a1f858fd0333 Signed-off-by: Avi Uday Reviewed-on: https://review.coreboot.org/c/coreboot/+/88941 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Pranava Y N Reviewed-by: Subrata Banik --- .../google/ocelot/variants/baseboard/ocelot/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb index 18708eb7f4..75c7641552 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb @@ -91,6 +91,8 @@ chip soc/intel/pantherlake register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "true" + register "disable_progress_bar" = "true" + device domain 0 on device ref dtt on end device ref npu on end