From 881fe9cef612da32d226be920018352fd513ccca Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 9 Jun 2025 16:21:27 -0500 Subject: [PATCH] soc/intel/alderlake: Add cpuid_to_adl mapping for Core 3 N350 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a mapping for the Core 3 N350 SoC, which has a MCH with PCI DID 0x4617, 8 efficiency cores, and a 7W TDP. This eliminates an error when setting power limits due to the missing entry: [ERROR] unknown SA ID: 0x4617, skipped power limits configuration TEST=build/boot starlabs/starlite_adl with ADL-N Core 3 N350 SoC. Change-Id: Ibd701ec5589a9a023a5538f470ff234a23249b45 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/88018 Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes Reviewed-by: Jérémy Compostella --- src/soc/intel/alderlake/chip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 3473b0643a..25e0f6ed28 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -162,6 +162,7 @@ static const struct { { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W }, + { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W }, { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W },