From 87f5d4c54a28727d1b844ff855dae3d034e2e10a Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 30 Aug 2025 16:11:24 +0200
Subject: [PATCH] tree: use boolean for PcieRpLtrEnable[]

PcieRpLtrEnable[] is a boolean, so use true false.

Change-Id: I3ccc64d7bb1a756efe8fc109c51c029a5483c316
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 .../sklkbl_thinkpad/variants/t480/overridetree.cb      | 10 +++++-----
 .../sklkbl_thinkpad/variants/t480s/overridetree.cb     | 10 +++++-----
 .../starlabs/starbook/variants/tgl/devicetree.cb       |  2 +-
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
index 14cbb7a050..3b05ae9fdc 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -41,7 +41,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
 			register "PcieRpAdvancedErrorReporting[0]"	= "1"
-			register "PcieRpLtrEnable[0]"			= "1"
+			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
 
@@ -59,7 +59,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[6]"		= "2"
 			register "PcieRpClkSrcNumber[6]"		= "2"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
-			register "PcieRpLtrEnable[6]"			= "1"
+			register "PcieRpLtrEnable[6]"			= "true"
 		end
 
 		# M.2 WWAN - x2
@@ -68,7 +68,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[4]"		= "3"
 			register "PcieRpClkSrcNumber[4]"		= "3"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
-			register "PcieRpLtrEnable[4]"			= "1"
+			register "PcieRpLtrEnable[4]"			= "true"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -77,7 +77,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[8]"		= "4"
 			register "PcieRpClkSrcNumber[8]"		= "4"
 			register "PcieRpAdvancedErrorReporting[8]"	= "1"
-			register "PcieRpLtrEnable[8]"			= "1"
+			register "PcieRpLtrEnable[8]"			= "true"
 			register "PcieRpHotPlug[8]"			= "1"
 		end
 
@@ -87,7 +87,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[10]"		= "5"
 			register "PcieRpClkSrcNumber[10]"		= "5"
 			register "PcieRpAdvancedErrorReporting[10]"	= "1"
-			register "PcieRpLtrEnable[10]"			= "1"
+			register "PcieRpLtrEnable[10]"			= "true"
 		end
 	end
 end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
index 50de1a09d7..6a933c42c8 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -41,7 +41,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
 			register "PcieRpAdvancedErrorReporting[0]"	= "1"
-			register "PcieRpLtrEnable[0]"			= "1"
+			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
 
@@ -51,7 +51,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[3]"		= "1"
 			register "PcieRpClkSrcNumber[3]"		= "1"
 			register "PcieRpAdvancedErrorReporting[3]"	= "1"
-			register "PcieRpLtrEnable[3]"			= "1"
+			register "PcieRpLtrEnable[3]"			= "true"
 		end
 
 		# Ethernet (clobbers RP8)
@@ -68,7 +68,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[6]"		= "3"
 			register "PcieRpClkSrcNumber[6]"		= "3"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
-			register "PcieRpLtrEnable[6]"			= "1"
+			register "PcieRpLtrEnable[6]"			= "true"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -77,7 +77,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[4]"		= "4"
 			register "PcieRpClkSrcNumber[4]"		= "4"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
-			register "PcieRpLtrEnable[4]"			= "1"
+			register "PcieRpLtrEnable[4]"			= "true"
 			register "PcieRpHotPlug[4]"			= "1"
 		end
 
@@ -87,7 +87,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqNumber[8]"		= "5"
 			register "PcieRpClkSrcNumber[8]"		= "5"
 			register "PcieRpAdvancedErrorReporting[8]"	= "1"
-			register "PcieRpLtrEnable[8]"			= "1"
+			register "PcieRpLtrEnable[8]"			= "true"
 		end
 	end
 end
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 16df1ef5c6..37dc077d2d 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -179,7 +179,7 @@ chip soc/intel/tigerlake
 		device ref uart2	on  end
 		device ref pcie_rp9	on
 			register "HybridStorageMode"			= "0"
-			register "PcieRpLtrEnable[8]"			= "1"
+			register "PcieRpLtrEnable[8]"			= "true"
 			register "PcieClkSrcUsage[3]"			= "0x08"
 			register "PcieClkSrcClkReq[3]"			= "3"
 			register "PcieRpSlotImplemented[8]"		= "true"