UPSTREAM: AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT

Vendorcode always does PCI MMCONF access once it is
enabled via MSR.

In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Reviewed-on: https://chromium-review.googlesource.com/416153
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/amd/pi/00630F01/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_PI_00630F01
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_PI_00630F01

src/cpu/amd/pi/00660F01/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_PI_00660F01
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_PI_00660F01

src/cpu/amd/pi/00670F00/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_PI_00670F00
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_PI_00670F00

src/cpu/amd/pi/00730F01/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_PI_00730F01
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_PI_00730F01