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drop one more version of doing serial uart output differently.

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coreboot made it kind of complicated to print a character on serial. Not quite
as complicated as UEFI, but too much for a good design. Fix it.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-12-17 00:08:21 +00:00 • committed by Stefan Reinauer
commit 85b0fa1ace
17 changed files with 248 additions and 231 deletions
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1
src/pc80/Makefile.inc
View file

@ -5,7 +5,6 @@ ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c
ramstage-y += keyboard.c
romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
romstage-$(CONFIG_CACHE_AS_RAM) += serial.c
romstage-$(CONFIG_USBDEBUG) += usbdebug_serial.c
subdirs-y += vga

119
src/pc80/serial.c
View file

@ -1,119 +0,0 @@
#include <lib.h> /* Prototypes */
#include <arch/io.h>
#include "pc80/mc146818rtc.h"
#if CONFIG_USE_OPTION_TABLE
#include "option_table.h"
#endif
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
#ifndef CONFIG_TTYS0_BAUD
#define CONFIG_TTYS0_BAUD 115200
#endif
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
#error Bad ttys0 baud rate
#endif
#ifndef CONFIG_TTYS0_DIV
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
#endif
/* Line Control Settings */
#ifndef CONFIG_TTYS0_LCS
/* Set 8bit, 1 stop bit, no parity */
#define CONFIG_TTYS0_LCS 0x3
#endif
#define UART_LCS CONFIG_TTYS0_LCS
#if CONFIG_CACHE_AS_RAM == 0
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
/* Control */
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_DLL 0x00
#define UART_DLM 0x01
/* Status */
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
static int uart_can_tx_byte(void)
{
return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
static void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
}
static void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
/* enable fifo's */
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
#if CONFIG_USE_OPTION_TABLE
static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
unsigned ttys0_div, ttys0_index;
ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
ttys0_index &= 7;
ttys0_div = divisor[ttys0_index];
outb(ttys0_div & 0xff, CONFIG_TTYS0_BASE + UART_DLL);
outb(0, CONFIG_TTYS0_BASE + UART_DLM);
#else
outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
#endif
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
#else
/* CONFIG_CACHE_AS_RAM == 1 */
extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
void uart_init(void)
{
#if CONFIG_USE_OPTION_TABLE
static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
unsigned ttys0_div, ttys0_index;
ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
ttys0_index &= 7;
ttys0_div = divisor[ttys0_index];
uart8250_init(CONFIG_TTYS0_BASE, ttys0_div, UART_LCS);
#else
uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, UART_LCS);
#endif
}
#endif