From 85ad36939f567c520e6dc93ea41c2cf3d9af109e Mon Sep 17 00:00:00 2001 From: Andrew Ip Date: Sun, 27 Apr 2003 15:00:31 +0000 Subject: [PATCH] e --- src/northbridge/via/vt8623/Config | 1 - src/northbridge/via/vt8623/northbridge.c | 97 ---------------- src/northbridge/via/vt8623/raminit.inc | 140 ----------------------- 3 files changed, 238 deletions(-) delete mode 100644 src/northbridge/via/vt8623/Config delete mode 100644 src/northbridge/via/vt8623/northbridge.c delete mode 100644 src/northbridge/via/vt8623/raminit.inc diff --git a/src/northbridge/via/vt8623/Config b/src/northbridge/via/vt8623/Config deleted file mode 100644 index 5191cb272f..0000000000 --- a/src/northbridge/via/vt8623/Config +++ /dev/null @@ -1 +0,0 @@ -object northbridge.o diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c deleted file mode 100644 index 61c6c806e9..0000000000 --- a/src/northbridge/via/vt8623/northbridge.c +++ /dev/null @@ -1,97 +0,0 @@ -#include -#include -#include -#include -#include - - -static unsigned long __sizeram(void) -{ - unsigned long totalmem; - unsigned char bank, mem, prevmem; - // fix me later -- there are two more banks at 0x56 and 0x57 - unsigned long firstbank = 0x5a, lastbank = 0x5d; - u8 sma_status, sma_size, sma_size_bits; - u8 val; - - struct pci_dev *pcidev; - - pcidev = pci_find_slot(0, PCI_DEVFN(0,0)); - - if (! pcidev) - return 0; - - pci_read_config_byte(pcidev, 0xe1, &sma_status); - sma_size_bits = (sma_status >> 4) & 0x07; - if (sma_size_bits > 7) - sma_size = 0; - else - sma_size = 0x01 << sma_size_bits; - - for(totalmem = mem = prevmem = 0, bank = firstbank; - bank <= lastbank; bank++) { - pci_read_config_byte(pcidev, bank, &mem); - // sanity check. If the mem value is < prevmem, - // that is an error, so skip this step. - if (mem < prevmem) { - printk_err("ERROR: bank 0x%x, mem 0x%x TOO SMALL\n", - bank, prevmem); - printk_err("Should be >= 0x%x\n", prevmem); - } else - totalmem += (mem - prevmem) * 16; - prevmem = mem; - } - - totalmem -= sma_size; - totalmem *= 1024; - - return totalmem; -} - -struct mem_range *sizeram(void) -{ - static struct mem_range mem[3]; - mem[0].basek = 0; - mem[0].sizek = 640; - mem[1].basek = 1024; - mem[1].sizek = __sizeram(); - mem[2].basek = 0; - mem[2].sizek = 0; - if (mem[1].sizek == 0) { - mem[1].sizek = 64*1024; - } - mem[1].sizek -= mem[1].basek; - return mem; -} - -#ifdef HAVE_FRAMEBUFFER -void framebuffer_on() -{ - unsigned long devfn; - u16 command; - - devfn = PCI_DEVFN(0, 1); - pcibios_read_config_word(0, devfn, 0x3e, &command); - command |= 0x08; - pcibios_write_config_word(0, devfn, 0x3e, command); -} -#endif - -/* - * This fixup is based on capturing values from an Award bios. Without - * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is - * slower than normal, ethernet drops packets). - * Apparently these registers govern some sort of bus master behavior. - */ -void northbridge_fixup(void) -{ - struct pci_dev *pcidev = pci_find_slot(0, PCI_DEVFN(0,0)); - - if (pcidev) { - pci_write_config_byte(pcidev, 0x70, 0xc0); - pci_write_config_byte(pcidev, 0x71, 0x88); - pci_write_config_byte(pcidev, 0x75, 0x01); - pci_write_config_byte(pcidev, 0x76, 0x52); - } -} - diff --git a/src/northbridge/via/vt8623/raminit.inc b/src/northbridge/via/vt8623/raminit.inc deleted file mode 100644 index 814d891a68..0000000000 --- a/src/northbridge/via/vt8623/raminit.inc +++ /dev/null @@ -1,140 +0,0 @@ -/* - * raminit.inc: Setting registers to their recommended values for vt8633 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#define loop200 $0x5000 -#define loop100 $0x2500 - -raminit: - intel_chip_post_macro(0x35) - - CS_WRITE($0x75, $0x08) - - /* since we only support epia-m at the moment, only ddr is supported */ - /* setup cpu */ - CS_WRITE($0x50, $0xc8) - CS_WRITE($0x51, $0xde) - CS_WRITE($0x52, $0xcf) - CS_WRITE($0x53, $0x88) - CS_WRITE($0x55, $0x07) - - /* DRAM MA Map Type */ - CS_WRITE($0x58, $0x71) - - /* DRAM bank 0 - 3 size = 512M */ - CS_WRITE($0x5a, $0x08) - CS_WRITE($0x5b, $0x08) - CS_WRITE($0x5c, $0x08) - CS_WRITE($0x5d, $0x08) - - /* set DRAM Timing for all banks */ - CS_WRITE($0x64, $0xe6) - - /* set DRAM type to DDR */ - CS_WRITE($0x60, $0x02) - - /* DRAM Arbitration Timer */ - CS_WRITE($0x65, $0x32) - CS_WRITE($0x66, $0x01) - CS_WRITE($0x68, $0x59) - - /* DRAM Frequency */ - CS_WRITE($0x54, $0xe0) - CS_WRITE($0x69, $0x2d) - - /* Enable CKE */ - CS_WRITE($0x6b, $0x10) - - /* Disable DRAM refresh */ - CS_WRITE($0x6a, $0x00) - - /* Set heavy drive */ - CS_WRITE($0x6d, $0x44) - - /* NOP Command Enable */ - CS_WRITE($0x6b, $0x01) - /* read a double word from any address of the dimm */ - movl %eax, %ds:(%esi) - DELAY(loop200) - - /* All bank Precharge Command Enable */ - CS_WRITE($0x6b, $0x02) - movl %eax, %ds:(%esi) - - /* MSR Enable */ - CS_WRITE($0x6b, $0x03) - /* read 0x2000h */ - movl $0x2000, %ecx - movl (%ecx), %eax - /* read 0x800h */ - movl $0x800, %ecx - movl (%ecx), %eax - - /* All banks Precharge Command Enable */ - CS_WRITE($0x6b, $0x02) - movl %eax, %ds:(%esi) - - /* CBR Cycle Enable */ - CS_WRITE($0x6b, $0x04) - /* Read 8 times */ - movl %eax, %ds:(%esi) - DELAY(loop100) - movl %eax, %ds:(%esi) - DELAY(loop100) - movl %eax, %ds:(%esi) - DELAY(loop100) - movl %eax, %ds:(%esi) - DELAY(loop100) - movl %eax, %ds:(%esi) - DELAY(loop100) - movl %eax, %ds:(%esi) - DELAY(loop100) - movl %eax, %ds:(%esi) - DELAY(loop100) - movl %eax, %ds:(%esi) - DELAY(loop100) - - /* MSR Enable */ - CS_WRITE($0x6b, $0x03) - /* 0x150 if CAS Latency 2 or 0x350 CAS Latency 2.5 */ - movl $0x350, %ecx - movl (%ecx), %eax - - /* Normal SDRAM Mode */ - CS_WRITE($0x6b, $0x58) - - /* Set the refreash rate */ - CS_WRITE($0x6a, $0x86) - - CS_WRITE($0x67, $0x39) - - /* pci */ - CS_WRITE($0x70, $0x82) - CS_WRITE($0x73, $0x01) - CS_WRITE($0x76, $0x50) - - CS_WRITE($0x71, $0xc8) - - /* graphics aperture base */ - CS_WRITE($0x13, $0xd0) - - CS_WRITE($0x56, $0x10) - CS_WRITE($0x57, $0x10) - - intel_chip_post_macro(0x36) -