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nb/intel/pineview: Use parallel MP init

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Remove guards around CPU code on which all platforms use parallel MP
init code.

This removes the option to disable HT siblings.

Tested on Foxconn D41S.

Change-Id: I89f7d514d75fe933c3a8858da37004419189674b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-04-10 15:18:38 +02:00 • committed by Patrick Georgi
commit 84fdda3812
6 changed files with 2 additions and 45 deletions
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17
src/cpu/intel/model_106cx/model_106cx_init.c
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@ -17,12 +17,9 @@
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/common/common.h>
@ -84,20 +81,10 @@ static void model_106cx_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
/* Update the microcode */
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs */
if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {
x86_setup_mtrrs();
x86_mtrr_check();
}
/* Enable the local CPU APICs */
setup_lapic();
@ -111,10 +98,6 @@ static void model_106cx_init(struct device *cpu)
configure_misc();
/* TODO: PIC thermal sensor control */
/* Start up my CPU siblings */
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {