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mb/google/brox: Reset XHCI controller while preparing for S5

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This patch calls `xhci_host_reset()` function to perform XHCI
controller reset. This is proactively pulled in to avoid any potential
timeouts when PMC sends an IPC command to disconnect the active USB
ports.

BUG=b:364158487
TEST=Build Brox BIOS image and boot to OS. Perform warm reset, cold
reset and suspend/resume cycle.

Change-Id: I33fd3aa13e81c7b1ae1ebf6674cc8ac1437ecc03
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2024-11-14 13:36:57 -07:00 • committed by Matt DeVillier
commit 845c861244
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/google/brox/smihandler.c
View file

@ -1,11 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <elog.h>
#include <baseboard/variants.h>
#include <intelblocks/smihandler.h>
#include <intelblocks/xhci.h>
#include <variant/ec.h>
void __weak variant_smi_sleep(u8 slp_typ) {}
@ -14,6 +16,12 @@ void mainboard_smi_sleep(u8 slp_typ)
{
variant_smi_sleep(slp_typ);
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
/*
* Workaround: Reset the XHCI controller prior to S5 to avoid
* PMC timeout error during poweron from S5.
*/
if (slp_typ == ACPI_S5)
xhci_host_reset();
}
int mainboard_smi_apmc(u8 apmc)