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soc/amd/common/block/cpu/noncar: Move BSS and DATA out of PT_LOAD

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Currently .bss and .data are within the PT_LOAD area of the
bootblock.elf and thus are placed and initialized at the correct spot
when PSP loads the BIOS Reset Image into DRAM.

On S3 resume PSP verifies that the "BIOS Reset Image" is unmodified
before it hands over control to such. Due to the use of BSS and DATA
within the BIOS Reset Image and the modifications of such at previous
boot the verification always fails.

This change moves '.bss' and '.data' out of the *first* PT_LOAD area
and moves it into a separate data_segment also marked PT_LOAD. Since
the second PT_LOAD is ignored by AMDCOMPRESS it doesn't end in the area
being verified at S3 resume. Since '.data' is now part of a separate
PT_LOAD a new region is inserted called '.datacopy' which is filled
by using objcopy. In turn the assembly code in bootblock will memcpy
'.datacopy' to '.data'.

TEST: Can still boot on amd/birman+ and on up/squared.

Change-Id: Id159ade3029060ce2ca6abcb723d5bdfe8841c3a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
Patrick Rudolph 2025-04-12 08:56:50 +02:00 • committed by Matt DeVillier
commit 82163aedc6
11 changed files with 117 additions and 23 deletions
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37
src/include/rules.h
View file

@ -274,13 +274,38 @@
#if ENV_X86
/* Indicates memory layout is determined with arch/x86/car.ld. */
#define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM))
#else
#define ENV_CACHE_AS_RAM 0
#endif
/* Indicates if the stage uses the _data and _bss regions defined in
* arch/x86/car.ld */
#define ENV_SEPARATE_DATA_AND_BSS (ENV_CACHE_AS_RAM && (ENV_BOOTBLOCK || !CONFIG(NO_XIP_EARLY_STAGES)))
/*
* ENV_SEPARATE_DATA_AND_BSS:
* When not set .data and .bss are in the same PT_LOAD segment defined
* in program.ld. When set .data and .bss are in a different PT_LOAD segment,
* defined outside of program.ld.
*
*
* On Intel APL the bootblock is loaded into a 4KiB SRAM.
* There's no space for .data and .bss.
* Once the bootblock code has set up CAR it will use it for .data and .bss.
* The other stages are load into CAR and doesn't need separation.
*
*
* On Non CAR AMD platforms the bootblock is loaded into DRAM on cold boot.
* On S3 the loader verifies that the bootblock has the same hash as on cold boot.
* As it must not change .data and .bss are not part of the PT_LOAD segment and
* the assembly code must set up .bss and load .data.
*
*
* On other platforms that use Cache As RAM:
* By default CAR implies separate .data and .bss.
* The stages execute from memory mapped SPI flash and use CAR as heap.
*/
#define ENV_SEPARATE_DATA_AND_BSS (ENV_BOOTBLOCK || (ENV_CACHE_AS_RAM && !CONFIG(NO_XIP_EARLY_STAGES)))
#else /* !ENV_X86 */
#define ENV_CACHE_AS_RAM 0
#define ENV_SEPARATE_DATA_AND_BSS 0
#endif
/* Currently ramstage has heap. */
#define ENV_HAS_HEAP_SECTION ENV_RAMSTAGE