From 81cbe11361e296900f53b77450ccce488bdd1c0d Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 8 Jun 2024 22:12:36 -0400 Subject: [PATCH] mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM Revert super I/O IRQ polarity settings replicated from OEM firmware back to its power-on defaults. With OEM settings COM 1/UART A/serial port 1 gets blocked right after the kernel boots. It no longer works or responds, which actually means the Linux boot process gets stuck forever when configured to write to ttyS0. Also revised the comment on another SIO setting to say it's being set for PECI. TEST=Not using these settings, I have not found any downside. Serial keeps working, sensors still work, S3 suspend/resume works correctly. Reported by Fabian and confirmed by Keith. Signed-off-by: Fabian Groffen Signed-off-by: Keith Hui Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75137 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: coreboot org Reviewed-by: Felix Singer --- .../asus/p8x7x-series/variants/p8z77-m/overridetree.cb | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index 41351b5bdd..9ff794b29f 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -40,12 +40,9 @@ chip northbridge/intel/sandybridge io 0x60 = 0x3f8 # COM1 address irq 0x70 = 4 # Below are global config settings to replicate OEM - drq 0x26 = 0x10 # Before accessing CR10/11/13/14, CR26:4 must be set to 1 - drq 0x13 = 0xff # IRQs 0-15 active low - drq 0x14 = 0xff drq 0x1a = 0x02 drq 0x1b = 0x60 - drq 0x2c = 0x00 # GP27, 3VSBSW#, No TSI + drq 0x2c = 0x00 # PECI end device pnp 2e.3 off end # UART B, IR device pnp 2e.5 on # PS2 KBC