From 81b977a2758d42471667e2cbe31f160dfda5bca4 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 27 Oct 2013 08:18:56 -0700 Subject: [PATCH] tegra124: clocks: Save some IOs in clock_enable_clear_reset. First, use the _set and _clr versions of the clk_enb and rst_dev registers to avoid having to both read and write to clear or set bits. Also, check to see if we're actually trying to set or clear bits before writing into those registers. BUG=None TEST=Built and booted on Nyan. BRANCH=None Change-Id: If3e5a0401bef7888e6af6395dd480901d25fdf09 Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/174845 Reviewed-by: Gabe Black Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/soc/nvidia/tegra124/clock.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 12ca61f889..5b8910b5f6 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -327,19 +327,18 @@ void clock_init(void) void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w) { - /* TODO: can (should?) we use the _SET and _CLR registers here? */ - setbits_le32(&clk_rst->clk_out_enb_l, l); - setbits_le32(&clk_rst->clk_out_enb_h, h); - setbits_le32(&clk_rst->clk_out_enb_u, u); - setbits_le32(&clk_rst->clk_out_enb_v, v); - setbits_le32(&clk_rst->clk_out_enb_w, w); + if (l) writel(l, &clk_rst->clk_enb_l_set); + if (h) writel(h, &clk_rst->clk_enb_h_set); + if (u) writel(u, &clk_rst->clk_enb_u_set); + if (v) writel(v, &clk_rst->clk_enb_v_set); + if (w) writel(w, &clk_rst->clk_enb_w_set); /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); - clrbits_le32(&clk_rst->rst_dev_l, l); - clrbits_le32(&clk_rst->rst_dev_h, h); - clrbits_le32(&clk_rst->rst_dev_u, u); - clrbits_le32(&clk_rst->rst_dev_v, v); - clrbits_le32(&clk_rst->rst_dev_w, w); + if (l) writel(l, &clk_rst->rst_dev_l_clr); + if (h) writel(h, &clk_rst->rst_dev_h_clr); + if (u) writel(u, &clk_rst->rst_dev_u_clr); + if (v) writel(v, &clk_rst->rst_dev_v_clr); + if (w) writel(w, &clk_rst->rst_dev_w_clr); }