From 80df8c336f0a8725358ecd8202a54c20cf00e65e Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 26 Aug 2025 16:06:53 -0700 Subject: [PATCH] mb/intel/ptlrvp: Update Kconfig for ptlrvp_chromeec4s and ptlrvp4es support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added support for new mainboard configurations, `ptlrvp_chromeec4es` and `ptlrvp4es`, to the Intel PTLRVP platform. These configurations extend the existing options for pre-production silicon of the Panther Lake SoC. BUG=none TEST=Build with new configurations to ensure successful compilation and correct feature selections. Change-Id: I3f716ab71a97d02b1694858d966f8111f18adff3 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/88997 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/mainboard/intel/ptlrvp/Kconfig | 39 ++++++++++++++++++++----- src/mainboard/intel/ptlrvp/Kconfig.name | 6 ++++ src/mainboard/intel/ptlrvp/Makefile.mk | 7 +++-- 3 files changed, 41 insertions(+), 11 deletions(-) diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig index 476313f60d..ec30b29491 100644 --- a/src/mainboard/intel/ptlrvp/Kconfig +++ b/src/mainboard/intel/ptlrvp/Kconfig @@ -56,8 +56,14 @@ config BOARD_INTEL_MODEL_PTLRVP config BOARD_INTEL_PTLRVP select BOARD_INTEL_MODEL_PTLRVP - select MAINBOARD_USES_IFD_EC_REGION select FW_CONFIG_SOURCE_CBFS + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_PTLRVP4ES + select BOARD_INTEL_MODEL_PTLRVP + select FW_CONFIG_SOURCE_CBFS + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON config BOARD_INTEL_PTLRVP_CHROMEEC select BOARD_INTEL_MODEL_PTLRVP @@ -73,6 +79,21 @@ config BOARD_INTEL_PTLRVP_CHROMEEC select MAINBOARD_USES_IFD_EC_REGION select TPM_GOOGLE_TI50 +config BOARD_INTEL_PTLRVP_CHROMEEC4ES + select BOARD_INTEL_MODEL_PTLRVP + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_MEC + select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS + select FW_CONFIG_SOURCE_CHROMEEC_CBI + select I2C_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_EC_REGION + select TPM_GOOGLE_TI50 + select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON + if BOARD_INTEL_PTLRVP_COMMON config BASEBOARD_DIR @@ -80,7 +101,7 @@ config BASEBOARD_DIR default "ptlrvp" config CHROMEOS - select EC_GOOGLE_CHROMEEC_SWITCHES if BOARD_INTEL_PTLRVP_CHROMEEC + select EC_GOOGLE_CHROMEEC_SWITCHES if EC_GOOGLE_CHROMEEC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC_MEC select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_MANUAL_RECOVERY @@ -102,11 +123,11 @@ config DIMM_SPD_SIZE config DRIVER_TPM_I2C_ADDR hex - default 0x50 if BOARD_INTEL_PTLRVP_CHROMEEC + default 0x50 if EC_GOOGLE_CHROMEEC config DRIVER_TPM_I2C_BUS hex - default 0x03 if BOARD_INTEL_PTLRVP_CHROMEEC + default 0x03 if EC_GOOGLE_CHROMEEC config HAVE_SLP_S0_GATE def_bool n @@ -120,7 +141,9 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Ptlrvp" if BOARD_INTEL_PTLRVP + default "Ptlrvp4es" if BOARD_INTEL_PTLRVP4ES default "Ptlrvp_chromeec" if BOARD_INTEL_PTLRVP_CHROMEEC + default "Ptlrvp_chromeec4es" if BOARD_INTEL_PTLRVP_CHROMEEC4ES config MEMORY_SOLDERDOWN def_bool n @@ -129,7 +152,7 @@ config MEMORY_SOLDERDOWN config TPM_TIS_ACPI_INTERRUPT int - default 47 if BOARD_INTEL_PTLRVP_CHROMEEC # GPE0_DW1_15 (GPP_D15) + default 47 if EC_GOOGLE_CHROMEEC # GPE0_DW1_15 (GPP_D15) # FIXME: update as per board schematics config UART_FOR_CONSOLE @@ -144,11 +167,11 @@ config VARIANT_DIR default "ptlrvp" if BOARD_INTEL_MODEL_PTLRVP config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_INTEL_PTLRVP - default "variants/\$(CONFIG_VARIANT_DIR)_chromeec/overridetree.cb" if BOARD_INTEL_PTLRVP_CHROMEEC + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_INTEL_PTLRVP || BOARD_INTEL_PTLRVP4ES + default "variants/\$(CONFIG_VARIANT_DIR)_chromeec/overridetree.cb" if BOARD_INTEL_PTLRVP_CHROMEEC || BOARD_INTEL_PTLRVP_CHROMEEC4ES config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA if BOARD_INTEL_PTLRVP + select VBOOT_MOCK_SECDATA if !EC_GOOGLE_CHROMEEC endif # BOARD_INTEL_PTLRVP_COMMON diff --git a/src/mainboard/intel/ptlrvp/Kconfig.name b/src/mainboard/intel/ptlrvp/Kconfig.name index 9bcf99b2f2..a8aebf12f0 100644 --- a/src/mainboard/intel/ptlrvp/Kconfig.name +++ b/src/mainboard/intel/ptlrvp/Kconfig.name @@ -5,5 +5,11 @@ comment "Ptlrvp" config BOARD_INTEL_PTLRVP bool "-> Ptlrvp" +config BOARD_INTEL_PTLRVP4ES + bool "-> Ptlrvp4es" + config BOARD_INTEL_PTLRVP_CHROMEEC bool "-> Google Chrome EC" + +config BOARD_INTEL_PTLRVP_CHROMEEC4ES + bool "-> Google Chrome EC for Early Silicon" diff --git a/src/mainboard/intel/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/Makefile.mk index d2c78f4411..37c7a5d2a2 100644 --- a/src/mainboard/intel/ptlrvp/Makefile.mk +++ b/src/mainboard/intel/ptlrvp/Makefile.mk @@ -3,17 +3,18 @@ bootblock-y += bootblock.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c +verstage-$(if $(filter y,$(CONFIG_EC_GOOGLE_CHROMEEC)),n,y) += intel.c romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c +romstage-$(if $(filter y,$(CONFIG_EC_GOOGLE_CHROMEEC)),n,y) += intel.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c -ramstage-$(CONFIG_BOARD_INTEL_PTLRVP) += intel.c +ramstage-$(if $(filter y,$(CONFIG_EC_GOOGLE_CHROMEEC)),n,y) += intel.c + smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c