From 807c9d0840acbc7ad0c1ee865fefc8ee10183c72 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Tue, 1 Apr 2025 17:27:32 +0530 Subject: [PATCH] mb/google/brya/var/mithrax: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on mithrax device and verify that the device suspends to S0ix. Change-Id: I5008ec5e153c3695b1d6aa1183515eba192deaa2 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/87060 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik Reviewed-by: Jayvik Desai --- .../google/brya/variants/mithrax/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 15bebe2a1a..6a85edf658 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -218,6 +218,15 @@ chip soc/intel/alderlake device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end #PCIE9-12 SSD device ref i2c0 on chip drivers/i2c/generic register "hid" = ""RTL5682""