From 800d3dbef4069a9e4d35e97af4617c944a82fb06 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Wed, 25 Mar 2026 21:20:22 +0530
Subject: [PATCH] soc/qualcomm/x1p42100: Support separate RO/RW CPUCP binaries

The CPUCP (CPU Control Processor) binary is currently stored
uncompressed in the RO region. To save space in the RO section
while maintaining fast boot performance in normal mode, split the
CPUCP CBFS entry into two distinct files:

1. cpucp_rw: Stored in FW_MAIN_A and FW_MAIN_B with no compression
   for performance.
2. cpucp_ro: Stored in the COREBOOT (RO) region with LZMA
   compression to save flash space.

Update the loading logic in cpucp_load_reset.c to select the
appropriate binary based on the current vboot mode (Normal vs.
Recovery).

BUG=None
TEST=Verified that CPUCP loads from 'cpucp_rw' during normal boot
and 'cpucp_ro' when vboot recovery is triggered.

Normal Mode:
```
[INFO ]  CBFS: Found 'fallback/cpucp_rw' @0xc8640 size 0x79244
         in mcache @0x8669d628
```

Recovery Mode:
```
[INFO ]  CBFS: Found 'fallback/cpucp_ro' @0xc8640 size 0x79244
         in mcache @0x8669d628
```

Change-Id: Iec5294beec4377b13f8b7354d86055d5907c6556
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/qualcomm/x1p42100/Makefile.mk        | 19 ++++++++++++++-----
 src/soc/qualcomm/x1p42100/cpucp_load_reset.c |  8 ++++++--
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index cfb8410e60..2fdade4c6a 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -222,11 +222,20 @@ cbfs-files-y += $(AOP_DEVCFG_META_CBFS)
 
 ################################################################################
 CPUCP_FILE := $(X1P42100_BLOB)/cpucp/cpucp.elf
-CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
-$(CPUCP_CBFS)-file := $(CPUCP_FILE)
-$(CPUCP_CBFS)-type := payload
-$(CPUCP_CBFS)-compression := none
-cbfs-files-y += $(CPUCP_CBFS)
+
+CPUCP_CBFS_RW := $(CONFIG_CBFS_PREFIX)/cpucp_rw
+regions-for-file-$(CPUCP_CBFS_RW) = FW_MAIN_A,FW_MAIN_B
+$(CPUCP_CBFS_RW)-file := $(CPUCP_FILE)
+$(CPUCP_CBFS_RW)-type := payload
+$(CPUCP_CBFS_RW)-compression := none
+cbfs-files-y += $(CPUCP_CBFS_RW)
+
+CPUCP_CBFS_RO := $(CONFIG_CBFS_PREFIX)/cpucp_ro
+regions-for-file-$(CPUCP_CBFS_RO) = COREBOOT
+$(CPUCP_CBFS_RO)-file := $(CPUCP_FILE)
+$(CPUCP_CBFS_RO)-type := payload
+$(CPUCP_CBFS_RO)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_CBFS_RO)
 
 ################################################################################
 # Rule to create cpucp_meta from cpucp.elf
diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
index 274c724724..80e3a39283 100644
--- a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
+++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
@@ -6,6 +6,7 @@
 #include <program_loading.h>
 #include <soc/cpucp.h>
 #include <device/mmio.h>
+#include <security/vboot/vboot_common.h>
 #include <soc/addressmap.h>
 #include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
@@ -24,8 +25,11 @@ void cpucp_fw_load_reset(void)
 
 	printk(BIOS_DEBUG, "SOC image: CPUCP DTBS image loaded successfully.\n");
 
-	struct prog cpucp_fw_prog =
-		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
+	const char *cpucp_name = (CONFIG(VBOOT) && !vboot_recovery_mode_enabled())
+			 ? CONFIG_CBFS_PREFIX "/cpucp_rw"
+			 : CONFIG_CBFS_PREFIX "/cpucp_ro";
+
+	struct prog cpucp_fw_prog = PROG_INIT(PROG_PAYLOAD, cpucp_name);
 
 	if (!selfload(&cpucp_fw_prog))
 		die("SOC image: CPUCP load failed");