erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

device/device.h: Rename busses for clarity

Browse source 
This renames bus to upstream and link_list to downstream.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2023-08-24 15:12:19 +02:00 • committed by Felix Held
commit 7fcd4d58ec
104 changed files with 343 additions and 348 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/common/block/acpi/pep.c
View file

@ -144,7 +144,7 @@ static enum acpi_device_sleep_states get_min_sleep_state(
case DEVICE_PATH_PCI:
/* skip external buses*/
if ((dev->bus->secondary != 0) || (!states_arr))
if ((dev->upstream->secondary != 0) || (!states_arr))
return ACPI_DEVICE_SLEEP_NONE;
for (size_t i = 0; i < size; i++)
if (states_arr[i].pci_dev == dev->path.pci.devfn)

4
src/soc/intel/common/block/lpc/lpc.c
View file

@ -102,10 +102,10 @@ static void pch_lpc_set_child_resources(struct device *dev)
{
struct device *child;
if (!dev->link_list)
if (!dev->downstream)
return;
for (child = dev->link_list->children; child; child = child->sibling)
for (child = dev->downstream->children; child; child = child->sibling)
pch_lpc_loop_resources(child);
}

6
src/soc/intel/common/block/pcie/rtd3/rtd3.c
View file

@ -140,7 +140,7 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp,
enum pcie_rp_type rp_type,
const struct device *dev)
{
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
acpigen_write_method_serialized("_ON", 0);
@ -224,7 +224,7 @@ pcie_rtd3_acpi_method_off(int pcie_rp,
const struct device *dev)
{
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
acpigen_write_method_serialized("_OFF", 0);
@ -385,7 +385,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev)
const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev);
static const char *const power_res_states[] = {"_PR0"};
const struct device *parent = dev->bus->dev;
const struct device *parent = dev->upstream->dev;
const char *scope = acpi_device_path(parent);
const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff);
const struct fieldlist fieldlist[] = {

2
src/soc/intel/common/block/usb4/pcie.c
View file

@ -19,7 +19,7 @@ static void usb4_pcie_acpi_fill_ssdt(const struct device *dev)
int port_id;
/* Get parent PCI device */
parent = dev->bus->dev;
parent = dev->upstream->dev;
if (!parent) {
printk(BIOS_ERR, "%s: Unable to find parent device\n", __func__);
return;

4
src/soc/intel/common/block/xhci/xhci.c
View file

@ -92,8 +92,8 @@ void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type,
return;
}
while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) {
while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) {
while ((hub = dev_bus_each_child(xhci->downstream, hub)) != NULL) {
while ((port = dev_bus_each_child(hub->downstream, port)) != NULL) {
enable = true;
config = config_of(port);
if (config->type == UPC_TYPE_INTERNAL) {