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device/device.h: Rename busses for clarity

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This renames bus to upstream and link_list to downstream.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2023-08-24 15:12:19 +02:00 • committed by Felix Held
commit 7fcd4d58ec
104 changed files with 343 additions and 348 deletions
Download patch file Download diff file Expand all files Collapse all files

20
src/northbridge/amd/pi/00730F01/northbridge.c
View file

@ -186,7 +186,7 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current;
ivhd_entry->type = type;
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
ivhd_entry->dte_setting = data;
*current += sizeof(ivrs_ivhd_generic_t);
} else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) {
@ -195,12 +195,12 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de
ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current;
ivhd_entry->type = type;
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8);
ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8);
ivhd_entry->dte_setting = data;
ivhd_entry->reserved1 = 0;
ivhd_entry->reserved2 = 0;
ivhd_entry->source_dev_id = parent->path.pci.devfn |
(parent->bus->secondary << 8);
(parent->upstream->secondary << 8);
*current += sizeof(ivrs_ivhd_alias_t);
}
@ -243,7 +243,7 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
if (dev->path.type == DEVICE_PATH_PCI) {
if ((dev->bus->secondary == 0x0) &&
if ((dev->upstream->secondary == 0x0) &&
(dev->path.pci.devfn == 0x0))
*root_level = depth;
@ -253,8 +253,8 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev,
}
}
if (dev->link_list) {
for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling)
if (dev->downstream) {
for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling)
add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level,
current, ivhd_length);
}
@ -290,12 +290,12 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_a
ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f;
ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11);
/* BDF <bus>:00.2 */
ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8);
ivhd_11->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
/* PCI Capability block 0x40 (type 0xf, "Secure device") */
ivhd_11->capability_offset = 0x40;
ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low;
ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high;
ivhd_11->pci_segment_group = nb_dev->bus->segment_group;
ivhd_11->pci_segment_group = nb_dev->upstream->segment_group;
ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info;
ivhd_11->iommu_attributes.perf_counters =
(IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf;
@ -358,12 +358,12 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
ivrs->ivhd.flags = ivrs_agesa->ivhd.flags;
ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd);
/* BDF <bus>:00.2 */
ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8);
ivrs->ivhd.device_id = 0x02 | (nb_dev->upstream->secondary << 8);
/* PCI Capability block 0x40 (type 0xf, "Secure device") */
ivrs->ivhd.capability_offset = 0x40;
ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low;
ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high;
ivrs->ivhd.pci_segment_group = nb_dev->bus->segment_group;
ivrs->ivhd.pci_segment_group = nb_dev->upstream->segment_group;
ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info;
ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info;
/* Enable EFR if supported */

2
src/northbridge/intel/e7505/northbridge.c
View file

@ -52,7 +52,7 @@ static void mch_domain_read_resources(struct device *dev)
static void mch_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
struct device_operations e7505_pci_domain_ops = {

2
src/northbridge/intel/gm45/northbridge.c
View file

@ -122,7 +122,7 @@ static void mch_domain_set_resources(struct device *dev)
report_resource_stored(dev, resource, "");
}
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void mch_domain_init(struct device *dev)

10
src/northbridge/intel/haswell/pcie.c
View file

@ -20,8 +20,8 @@ static const char *pcie_acpi_name(const struct device *dev)
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
assert(dev->bus);
if (dev->bus->secondary == 0)
assert(dev->upstream);
if (dev->upstream->secondary == 0)
switch (dev->path.pci.devfn) {
case PCI_DEVFN(1, 0):
return "PEGP";
@ -31,12 +31,12 @@ static const char *pcie_acpi_name(const struct device *dev)
return "PEG2";
};
struct device *const port = dev->bus->dev;
struct device *const port = dev->upstream->dev;
assert(port);
assert(port->bus);
assert(port->upstream);
if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
port->bus->secondary == 0 &&
port->upstream->secondary == 0 &&
(port->path.pci.devfn == PCI_DEVFN(1, 0) ||
port->path.pci.devfn == PCI_DEVFN(1, 1) ||
port->path.pci.devfn == PCI_DEVFN(1, 2)))

4
src/northbridge/intel/i440bx/northbridge.c
View file

@ -34,8 +34,8 @@ static void i440bx_domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
pci_tolm = find_pci_tolm(dev->downstream);
mc_dev = dev->downstream->children;
if (mc_dev) {
unsigned long tomk, tolmk;
int idx;

4
src/northbridge/intel/i945/northbridge.c
View file

@ -26,7 +26,7 @@ static void mch_domain_read_resources(struct device *dev)
/* Can we find out how much memory we can use at most
* this way?
*/
pci_tolm = find_pci_tolm(dev->link_list);
pci_tolm = find_pci_tolm(dev->downstream);
printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
tolud = pci_read_config8(d0f0, TOLUD) << 24;
@ -65,7 +65,7 @@ static void mch_domain_set_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next)
report_resource_stored(dev, res, "");
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static const char *northbridge_acpi_name(const struct device *dev)

2
src/northbridge/intel/pineview/northbridge.c
View file

@ -108,7 +108,7 @@ static void mch_domain_set_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next)
report_resource_stored(dev, res, "");
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void mch_domain_init(struct device *dev)

10
src/northbridge/intel/sandybridge/pcie.c
View file

@ -13,8 +13,8 @@ static const char *pcie_acpi_name(const struct device *dev)
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
assert(dev->bus);
if (dev->bus->secondary == 0)
assert(dev->upstream);
if (dev->upstream->secondary == 0)
switch (dev->path.pci.devfn) {
case PCI_DEVFN(1, 0):
return "PEGP";
@ -26,12 +26,12 @@ static const char *pcie_acpi_name(const struct device *dev)
return "PEG6";
};
struct device *const port = dev->bus->dev;
struct device *const port = dev->upstream->dev;
assert(port);
assert(port->bus);
assert(port->upstream);
if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
port->bus->secondary == 0 &&
port->upstream->secondary == 0 &&
(port->path.pci.devfn == PCI_DEVFN(1, 0) ||
port->path.pci.devfn == PCI_DEVFN(1, 1) ||
port->path.pci.devfn == PCI_DEVFN(1, 2) ||

2
src/northbridge/intel/x4x/northbridge.c
View file

@ -72,7 +72,7 @@ static void mch_domain_set_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next)
report_resource_stored(dev, res, "");
assign_resources(dev->link_list);
assign_resources(dev->downstream);
}
static void mch_domain_init(struct device *dev)