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baytrail: Switch to per-device ACPI

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Change-Id: I6a1b1daa291298c85e14f89aa47a0693837cec6f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7037
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Vladimir Serbinenko 2014-10-08 22:56:27 +02:00
commit 7fb149dce1
17 changed files with 148 additions and 761 deletions
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1
src/soc/intel/baytrail/Kconfig
View file

@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select UDELAY_TSC
select SOC_INTEL_COMMON
select PER_DEVICE_ACPI_TABLES
config BOOTBLOCK_CPU_INIT
string

53
src/soc/intel/baytrail/acpi.c
View file

@ -295,24 +295,20 @@ static acpi_tstate_t baytrail_tss_table[] = {
{ 13, 125, 0, 0x12, 0 },
};
static int generate_T_state_entries(int core, int cores_per_package)
static void generate_T_state_entries(int core, int cores_per_package)
{
int len;
/* Indicate SW_ALL coordination for T-states */
len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */
len += acpigen_write_empty_PTC();
acpigen_write_empty_PTC();
/* Set NVS controlled T-state limit */
len += acpigen_write_TPC("\\TLVL");
acpigen_write_TPC("\\TLVL");
/* Write TSS table for MSR access */
len += acpigen_write_TSS_package(
acpigen_write_TSS_package(
ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table);
return len;
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
@ -336,9 +332,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
return (int)power;
}
static int generate_P_state_entries(int core, int cores_per_package)
static void generate_P_state_entries(int core, int cores_per_package)
{
int len, len_pss;
int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
int coord_type, power_max, power_unit, num_entries;
int ratio, power, clock, clock_max;
@ -366,16 +361,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */
len = acpigen_write_empty_PCT();
acpigen_write_empty_PCT();
/* Write _PPC with NVS specified limit on supported P-state */
len += acpigen_write_PPC_NVS();
acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
len += acpigen_write_PSD_package(core, 1, coord_type);
acpigen_write_PSD_package(core, 1, coord_type);
/* Add P-state entries in _PSS table */
len += acpigen_write_name("_PSS");
acpigen_write_name("_PSS");
/* Determine ratio points */
ratio_step = 1;
@ -388,14 +383,14 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* P[T] is Turbo state if enabled */
if (get_turbo_state() == TURBO_ENABLED) {
/* _PSS package count including Turbo */
len_pss = acpigen_write_package(num_entries + 2);
acpigen_write_package(num_entries + 2);
ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
control_status = (ratio_turbo << 8) | vid_turbo;
/* Add entry for Turbo ratio */
len_pss += acpigen_write_PSS_package(
acpigen_write_PSS_package(
clock_max + 1, /*MHz*/
power_max, /*mW*/
10, /*lat1*/
@ -404,14 +399,14 @@ static int generate_P_state_entries(int core, int cores_per_package)
control_status); /*status*/
} else {
/* _PSS package count without Turbo */
len_pss = acpigen_write_package(num_entries + 1);
acpigen_write_package(num_entries + 1);
ratio_turbo = ratio_max;
vid_turbo = vid_max;
}
/* First regular entry is max non-turbo ratio */
control_status = (ratio_max << 8) | vid_max;
len_pss += acpigen_write_PSS_package(
acpigen_write_PSS_package(
clock_max, /*MHz*/
power_max, /*mW*/
10, /*lat1*/
@ -439,7 +434,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
clock = (ratio * pattrs->bclk_khz) / 1000;
control_status = (ratio << 8) | (vid & 0xff);
len_pss += acpigen_write_PSS_package(
acpigen_write_PSS_package(
clock, /*MHz*/
power, /*mW*/
10, /*lat1*/
@ -449,15 +444,12 @@ static int generate_P_state_entries(int core, int cores_per_package)
}
/* Fix package length */
len_pss--;
acpigen_patch_len(len_pss);
return len + len_pss;
acpigen_pop_len();
}
void generate_cpu_entries(void)
{
int len_pr, core;
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
const struct pattrs *pattrs = pattrs_get();
@ -468,23 +460,22 @@ void generate_cpu_entries(void)
}
/* Generate processor \_PR.CPUx */
len_pr = acpigen_write_processor(
acpigen_write_processor(
core, pcontrol_blk, plen);
/* Generate P-state tables */
len_pr += generate_P_state_entries(
generate_P_state_entries(
core, pattrs->num_cpus);
/* Generate C-state tables */
len_pr += acpigen_write_CST_package(
acpigen_write_CST_package(
cstate_map, ARRAY_SIZE(cstate_map));
/* Generate T-state tables */
len_pr += generate_T_state_entries(
generate_T_state_entries(
core, pattrs->num_cpus);
len_pr--;
acpigen_patch_len(len_pr);
acpigen_pop_len();
}
}

3
src/soc/intel/baytrail/acpi/globalnvs.asl
View file

@ -29,7 +29,8 @@ Name(\PICM, 0) // IOAPIC/8259
*/
OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
External(NVSA)
OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */

1
src/soc/intel/baytrail/include/soc/nvs.h
View file

@ -70,6 +70,7 @@ typedef struct {
device_nvs_t dev;
} __attribute__((packed)) global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);

2
src/soc/intel/baytrail/northcluster.c
View file

@ -23,6 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <arch/acpi.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
@ -133,6 +134,7 @@ static void nc_read_resources(device_t dev)
static struct device_operations nc_ops = {
.read_resources = nc_read_resources,
.acpi_fill_ssdt_generator = generate_cpu_entries,
.set_resources = NULL,
.enable_resources = NULL,
.init = NULL,

30
src/soc/intel/baytrail/southcluster.c
View file

@ -40,6 +40,9 @@
#include <soc/ramstage.h>
#include <soc/spi.h>
#include "chip.h"
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <cpu/cpu.h>
static inline void
add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
@ -510,9 +513,36 @@ void southcluster_enable_dev(device_t dev)
}
}
static void southcluster_inject_dsdt(void)
{
global_nvs_t *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);
acpi_save_gnvs((unsigned long)gnvs);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);
acpigen_pop_len();
}
}
static struct device_operations device_ops = {
.read_resources = sc_read_resources,
.set_resources = pci_dev_set_resources,
.acpi_inject_dsdt_generator = southcluster_inject_dsdt,
.write_acpi_tables = acpi_write_hpet,
.enable_resources = NULL,
.init = sc_init,
.enable = southcluster_enable_dev,

1
src/soc/intel/fsp_baytrail/Kconfig
View file

@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select ROMSTAGE_RTC_INIT
select PER_DEVICE_ACPI_TABLES
config SOC_INTEL_FSP_BAYTRAIL_MD
bool

93
src/soc/intel/fsp_baytrail/acpi.c
View file

@ -46,6 +46,7 @@
#include <baytrail/msr.h>
#include <baytrail/pattrs.h>
#include <baytrail/pmc.h>
#include <cpu/cpu.h>
#include <cbmem.h>
#include "chip.h"
@ -401,9 +402,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
return (int)power;
}
static int generate_P_state_entries(int core, int cores_per_package)
static void generate_P_state_entries(int core, int cores_per_package)
{
int len, len_pss;
int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
int coord_type, power_max, power_unit, num_entries;
int ratio, power, clock, clock_max;
@ -431,16 +431,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */
len = acpigen_write_empty_PCT();
acpigen_write_empty_PCT();
/* Write _PPC with NVS specified limit on supported P-state */
len += acpigen_write_PPC_NVS();
acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
len += acpigen_write_PSD_package(core, 1, coord_type);
acpigen_write_PSD_package(core, 1, coord_type);
/* Add P-state entries in _PSS table */
len += acpigen_write_name("_PSS");
acpigen_write_name("_PSS");
/* Determine ratio points */
ratio_step = 1;
@ -453,14 +453,14 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* P[T] is Turbo state if enabled */
if (get_turbo_state() == TURBO_ENABLED) {
/* _PSS package count including Turbo */
len_pss = acpigen_write_package(num_entries + 2);
acpigen_write_package(num_entries + 2);
ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
control_status = (ratio_turbo << 8) | vid_turbo;
/* Add entry for Turbo ratio */
len_pss += acpigen_write_PSS_package(
acpigen_write_PSS_package(
clock_max + 1, /*MHz*/
power_max, /*mW*/
10, /*lat1*/
@ -469,14 +469,14 @@ static int generate_P_state_entries(int core, int cores_per_package)
control_status); /*status*/
} else {
/* _PSS package count without Turbo */
len_pss = acpigen_write_package(num_entries + 1);
acpigen_write_package(num_entries + 1);
ratio_turbo = ratio_max;
vid_turbo = vid_max;
}
/* First regular entry is max non-turbo ratio */
control_status = (ratio_max << 8) | vid_max;
len_pss += acpigen_write_PSS_package(
acpigen_write_PSS_package(
clock_max, /*MHz*/
power_max, /*mW*/
10, /*lat1*/
@ -504,7 +504,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
clock = (ratio * pattrs->bclk_khz) / 1000;
control_status = (ratio << 8) | (vid & 0xff);
len_pss += acpigen_write_PSS_package(
acpigen_write_PSS_package(
clock, /*MHz*/
power, /*mW*/
10, /*lat1*/
@ -514,15 +514,12 @@ static int generate_P_state_entries(int core, int cores_per_package)
}
/* Fix package length */
len_pss--;
acpigen_patch_len(len_pss);
return len + len_pss;
acpigen_pop_len();
}
void generate_cpu_entries(void)
{
int len_pr, core;
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
const struct pattrs *pattrs = pattrs_get();
@ -533,23 +530,22 @@ void generate_cpu_entries(void)
}
/* Generate processor \_PR.CPUx */
len_pr = acpigen_write_processor(
acpigen_write_processor(
core, pcontrol_blk, plen);
/* Generate P-state tables */
len_pr += generate_P_state_entries(
generate_P_state_entries(
core, pattrs->num_cpus);
/* Generate C-state tables */
len_pr += acpigen_write_CST_package(
acpigen_write_CST_package(
cstate_map, ARRAY_SIZE(cstate_map));
/* Generate T-state tables */
len_pr += generate_T_state_entries(
generate_T_state_entries(
core, pattrs->num_cpus);
len_pr--;
acpigen_patch_len(len_pr);
acpigen_pop_len();
}
}
@ -574,3 +570,56 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
return current;
}
#define ALIGN_CURRENT current = (ALIGN(current, 16))
unsigned long southcluster_write_acpi_tables(unsigned long current,
struct acpi_rsdp *rsdp)
{
acpi_header_t *ssdt2;
current = acpi_write_hpet(current, rsdp);
ALIGN_CURRENT;
ssdt2 = (acpi_header_t *)current;
memset(ssdt2, 0, sizeof(acpi_header_t));
acpi_create_serialio_ssdt(ssdt2);
if (ssdt2->length) {
current += ssdt2->length;
acpi_add_table(rsdp, ssdt2);
printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2,
ssdt2->length);
ALIGN_CURRENT;
} else {
ssdt2 = NULL;
printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n");
}
printk(BIOS_DEBUG, "current = %lx\n", current);
return current;
}
void southcluster_inject_dsdt(void)
{
global_nvs_t *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);
acpi_save_gnvs((unsigned long)gnvs);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);
acpigen_pop_len();
}
}

3
src/soc/intel/fsp_baytrail/acpi/globalnvs.asl
View file

@ -29,7 +29,8 @@ Name(\PICM, 0) // IOAPIC/8259
*/
OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
External(NVSA)
OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */

3
src/soc/intel/fsp_baytrail/baytrail/acpi.h
View file

@ -29,5 +29,8 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long southcluster_write_acpi_tables(unsigned long current,
struct acpi_rsdp *rsdp);
void southcluster_inject_dsdt(void);
#endif /* _BAYTRAIL_ACPI_H_ */

1
src/soc/intel/fsp_baytrail/baytrail/nvs.h
View file

@ -68,6 +68,7 @@ typedef struct {
device_nvs_t dev;
} __attribute__((packed)) global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);

3
src/soc/intel/fsp_baytrail/northcluster.c
View file

@ -32,7 +32,7 @@
#include <cbmem.h>
#include <baytrail/baytrail.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <arch/acpi.h>
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
@ -201,6 +201,7 @@ static void nc_enable(device_t dev)
static struct device_operations nc_ops = {
.read_resources = nc_read_resources,
.acpi_fill_ssdt_generator = generate_cpu_entries,
.set_resources = NULL,
.enable_resources = NULL,
.init = NULL,

6
src/soc/intel/fsp_baytrail/southcluster.c
View file

@ -39,10 +39,14 @@
#include <baytrail/irq.h>
#include <baytrail/lpc.h>
#include <baytrail/nvs.h>
#include <baytrail/acpi.h>
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
#include "chip.h"
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <cpu/cpu.h>
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
@ -598,6 +602,8 @@ void southcluster_enable_dev(device_t dev)
static struct device_operations device_ops = {
.read_resources = sc_read_resources,
.set_resources = pci_dev_set_resources,
.acpi_inject_dsdt_generator = southcluster_inject_dsdt,
.write_acpi_tables = southcluster_write_acpi_tables,
.enable_resources = NULL,
.init = sc_init,
.enable = southcluster_enable_dev,