erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULT

Browse source 
Boards with this chipset do not have any reference of
MMCONF_BASE_ADDRESS being written to chipset registers.
Either board support is already broken or FSP takes
care of this early and Kconfig lacks the notice that
this parameter must match with the chosen FSP binary.

CPU bootblock associated with this chipset uses
exclusive PCI IO access already.

Untested.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17547
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08
Reviewed-on: https://chromium-review.googlesource.com/417088
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-29 16:26:14 +02:00 • committed by chrome-bot
commit 7f941707b2
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/northbridge/intel/fsp_rangeley/Kconfig
View file

@ -17,7 +17,7 @@
config NORTHBRIDGE_INTEL_FSP_RANGELEY
bool
select CPU_INTEL_FSP_MODEL_406DX
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
if NORTHBRIDGE_INTEL_FSP_RANGELEY