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soc/intel/*: Add CFR option to enable/disable the Intel iGPU

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TEST=Build and boot to OS. Verify functions work. (skylake)

Change-Id: I9d25c04302d23afd9b95625ddf03dfeee2fdf7c2
Signed-off-by: Ulysse Ballesteros <ulysse.ballesteros@outlook.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This commit is contained in:
Ulysse Ballesteros 2025-10-26 22:26:43 +01:00 • committed by Matt DeVillier
commit 7f93e2fe29
12 changed files with 89 additions and 17 deletions
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16
src/soc/intel/alderlake/include/soc/cfr.h
View file

@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
/* IGD Enabled */
static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
.opt_name = "igd_enabled",
.ui_name = "Enable the Intel iGPU",
.ui_helptext = "Enable or disable the Intel iGPU",
.default_value = !CONFIG(SOC_INTEL_DISABLE_IGD),
.values = (const struct sm_enum_value[]) {
{ "Disabled", 0 },
{ "Enabled", 1 },
SM_ENUM_VALUE_END },
});
/* IGD Aperture Size */
static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
.opt_name = "igd_aperture_size",
@ -39,7 +51,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
{ " 512 MB", IGD_AP_SZ_512MB },
#endif
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* IGD DVMT pre-allocated memory */
static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@ -55,7 +67,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
{ "128 MB", IGD_SM_128MB },
{ "160 MB", IGD_SM_160MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* Legacy 8254 Timer */
static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({

2
src/soc/intel/alderlake/romstage/fsp_params.c
View file

@ -152,7 +152,7 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
[DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
[DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
};
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
if (m_cfg->InternalGfx) {
/* IGD is enabled, set IGD stolen size to 60MB. */
m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);

16
src/soc/intel/cannonlake/include/soc/cfr.h
View file

@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
/* IGD Enabled */
static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
.opt_name = "igd_enabled",
.ui_name = "Enable the Intel iGPU",
.ui_helptext = "Enable or disable the Intel iGPU",
.default_value = !CONFIG(SOC_INTEL_DISABLE_IGD),
.values = (const struct sm_enum_value[]) {
{ "Disabled", 0 },
{ "Enabled", 1 },
SM_ENUM_VALUE_END },
});
/* IGD Aperture Size */
static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
.opt_name = "igd_aperture_size",
@ -33,7 +45,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
{ "256 MB", IGD_AP_SZ_256MB },
{ "512 MB", IGD_AP_SZ_512MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* IGD DVMT pre-allocated memory */
static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@ -47,7 +59,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
{ "96 MB", IGD_SM_96MB },
{ "128 MB", IGD_SM_128MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* Legacy 8254 Timer */
static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({

2
src/soc/intel/cannonlake/romstage/fsp_params.c
View file

@ -34,7 +34,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
* Probe for no IGD and disable InternalGfx and panel power to prevent a
* crash in FSP-M.
*/
const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
const bool igd_on = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
/* Set IGD stolen size to 64MB. */
m_cfg->InternalGfx = 1;

16
src/soc/intel/jasperlake/include/soc/cfr.h
View file

@ -10,6 +10,18 @@
#include <drivers/option/cfr_frontend.h>
#include <soc/soc_chip.h>
/* IGD Enabled */
static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
.opt_name = "igd_enabled",
.ui_name = "Enable the Intel iGPU",
.ui_helptext = "Enable or disable the Intel iGPU",
.default_value = !CONFIG(SOC_INTEL_DISABLE_IGD),
.values = (const struct sm_enum_value[]) {
{ "Disabled", 0 },
{ "Enabled", 1 },
SM_ENUM_VALUE_END },
});
/* IGD Aperture Size */
static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
.opt_name = "igd_aperture_size",
@ -21,7 +33,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
{ " 256 MB", IGD_AP_SZ_256MB },
{ " 512 MB", IGD_AP_SZ_512MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* IGD DVMT pre-allocated memory */
static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@ -37,7 +49,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
{ "128 MB", IGD_SM_128MB },
{ "160 MB", IGD_SM_160MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* Legacy 8254 Timer */
static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({

2
src/soc/intel/jasperlake/romstage/fsp_params.c
View file

@ -19,7 +19,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
{
unsigned int i;
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
if (m_cfg->InternalGfx) {
/* IGD is enabled, set IGD stolen size to 60MB. */

14
src/soc/intel/meteorlake/include/soc/cfr.h
View file

@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
/* IGD Enabled */
static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
.opt_name = "igd_enabled",
.ui_name = "Enable the Intel iGPU",
.ui_helptext = "Enable or disable the Intel iGPU",
.default_value = !CONFIG(SOC_INTEL_DISABLE_IGD),
.values = (const struct sm_enum_value[]) {
{ "Disabled", 0 },
{ "Enabled", 1 },
SM_ENUM_VALUE_END },
});
/* IGD DVMT pre-allocated memory */
static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
.opt_name = "igd_dvmt_prealloc",
@ -35,7 +47,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
{ "128 MB", IGD_SM_128MB },
{ "160 MB", IGD_SM_160MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* Legacy 8254 Timer */
static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({

2
src/soc/intel/meteorlake/romstage/fsp_params.c
View file

@ -123,7 +123,7 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
[DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
[DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
};
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD);
m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(PCI_DEVFN_IGD);
if (m_cfg->InternalGfx) {
/* IGD is enabled, set IGD stolen size to 128MB. */
m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_128MB);

16
src/soc/intel/skylake/include/soc/cfr.h
View file

@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
/* IGD Enabled */
static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
.opt_name = "igd_enabled",
.ui_name = "Enable the Intel iGPU",
.ui_helptext = "Enable or disable the Intel iGPU",
.default_value = !CONFIG(SOC_INTEL_DISABLE_IGD),
.values = (const struct sm_enum_value[]) {
{ "Disabled", 0 },
{ "Enabled", 1 },
SM_ENUM_VALUE_END },
});
/* IGD Aperture Size */
static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
.opt_name = "igd_aperture_size",
@ -33,7 +45,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
{ "256 MB", IGD_AP_SZ_256MB },
{ "512 MB", IGD_AP_SZ_512MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* IGD DVMT pre-allocated memory */
static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@ -47,7 +59,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
{ "96 MB", IGD_SM_96MB },
{ "128 MB", IGD_SM_128MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* Legacy 8254 Timer */
static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({

2
src/soc/intel/skylake/romstage/fsp_params.c
View file

@ -104,7 +104,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_skylake_config *config)
{
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
/*
* If iGPU is enabled, set IGD stolen size to 64MB. The FBC

16
src/soc/intel/tigerlake/include/soc/cfr.h
View file

@ -22,6 +22,18 @@ static const struct sm_object hyper_threading = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
/* IGD Enabled */
static const struct sm_object igd_enabled = SM_DECLARE_ENUM({
.opt_name = "igd_enabled",
.ui_name = "Enable the Intel iGPU",
.ui_helptext = "Enable or disable the Intel iGPU",
.default_value = !CONFIG(SOC_INTEL_DISABLE_IGD),
.values = (const struct sm_enum_value[]) {
{ "Disabled", 0 },
{ "Enabled", 1 },
SM_ENUM_VALUE_END },
});
/* IGD Aperture Size */
static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
.opt_name = "igd_aperture_size",
@ -39,7 +51,7 @@ static const struct sm_object igd_aperture = SM_DECLARE_ENUM({
{ " 512 MB", IGD_AP_SZ_512MB },
#endif
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* IGD DVMT pre-allocated memory */
static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
@ -55,7 +67,7 @@ static const struct sm_object igd_dvmt = SM_DECLARE_ENUM({
{ "128 MB", IGD_SM_128MB },
{ "160 MB", IGD_SM_160MB },
SM_ENUM_VALUE_END },
});
}, WITH_DEP_VALUES(&igd_enabled, 1));
/* Legacy 8254 Timer */
static const struct sm_object legacy_8254_timer = SM_DECLARE_ENUM({

2
src/soc/intel/tigerlake/romstage/fsp_params.c
View file

@ -27,7 +27,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
m_cfg->InternalGfx = get_uint_option("igd_enabled", !CONFIG(SOC_INTEL_DISABLE_IGD)) && is_devfn_enabled(SA_DEVFN_IGD);
if (m_cfg->InternalGfx) {
/* IGD is enabled, set IGD stolen size to 60MB. */