erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Add support to enable/disable builtin GbE

Browse source 
In case we are going to use this in future designs.

BUG=none
TEST=none
BRANCH=none

Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/55844
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Stefan Reinauer 2013-05-20 16:23:40 -07:00 • committed by ChromeBot
commit 7f588e7d62
2 changed files with 4 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/northbridge/intel/haswell/pei_data.h
View file

@ -31,7 +31,7 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 10
#define PEI_VERSION 11
struct pei_data
{
@ -53,6 +53,7 @@ struct pei_data
uint8_t spd_addresses[4];
int boot_mode;
int ec_present;
int gbe_enable;
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel

3
src/northbridge/intel/sandybridge/pei_data.h
View file

@ -38,7 +38,7 @@ typedef struct {
} pch_usb3_controller_settings;
typedef void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 5
#define PEI_VERSION 6
struct pei_data
{
@ -61,6 +61,7 @@ struct pei_data
uint8_t ts_addresses[4];
int boot_mode;
int ec_present;
int gbe_enable;
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel