From 7e706dc02783fae97a96a58cc54ec22d2633c36f Mon Sep 17 00:00:00 2001
From: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Date: Tue, 25 Mar 2025 11:07:03 -0300
Subject: [PATCH] mb/amb/crater: Clean up port descriptors

Use defines to create dxio descriptors as other mainboards.

Change-Id: I09e8a9fc37a7b775b76a3d8e5faaee7828f99000
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87220
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../amd/crater/port_descriptors_renoir.c      | 68 ++++++++++---------
 1 file changed, 36 insertions(+), 32 deletions(-)

diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c
index bcddf1e33e..757dab1b49 100644
--- a/src/mainboard/amd/crater/port_descriptors_renoir.c
+++ b/src/mainboard/amd/crater/port_descriptors_renoir.c
@@ -20,38 +20,37 @@
 
 #define CRATER_REVB     0x42
 
-static const fsp_dxio_descriptor crater_dxio_descriptors[] = {
-	{ /* MXM */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 16,
-		.end_logical_lane = 23,
-		.device_number = 1,
-		.function_number = 1,
-		.link_aspm = ASPM_L1,
-		.link_aspm_L1_1 = true,
-		.link_aspm_L1_2 = true,
-		.turn_off_unused_lanes = false,
-		.clk_req = CLK_REQ0,
-		.gpio_group_id = GPIO_4,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-	{ /* SSD */
-		.engine_type = PCIE_ENGINE,
-		.port_present = true,
-		.start_logical_lane = 8,
-		.end_logical_lane = 11,
-		.device_number = 2,
-		.function_number = 4,
-		.link_aspm = ASPM_DISABLED,
-		.link_aspm_L1_1 = false,
-		.link_aspm_L1_2 = false,
-		.turn_off_unused_lanes = false,
-		.clk_req = CLK_REQ3,
-		.gpio_group_id = GPIO_27,
-		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
-	},
-};
+#define mxm_dxio_descriptor {	\
+	.engine_type = PCIE_ENGINE, \
+	.port_present = true, \
+	.start_logical_lane = 16, \
+	.end_logical_lane = 23, \
+	.device_number = 1, \
+	.function_number = 1, \
+	.link_aspm = ASPM_L1, \
+	.link_aspm_L1_1 = true, \
+	.link_aspm_L1_2 = true, \
+	.turn_off_unused_lanes = false, \
+	.clk_req = CLK_REQ0, \
+	.gpio_group_id = GPIO_4, \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
+}
+
+#define ssd_dxio_descriptor { \
+	.engine_type = PCIE_ENGINE, \
+	.port_present = true, \
+	.start_logical_lane = 8, \
+	.end_logical_lane = 11, \
+	.device_number = 2, \
+	.function_number = 4, \
+	.link_aspm = ASPM_DISABLED, \
+	.link_aspm_L1_1 = false, \
+	.link_aspm_L1_2 = false, \
+	.turn_off_unused_lanes = false, \
+	.clk_req = CLK_REQ3, \
+	.gpio_group_id = GPIO_27, \
+	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}, \
+}
 
 static fsp_ddi_descriptor crater_ddi_descriptors[] = {
 	{ /* DDI0 - DP */
@@ -102,6 +101,11 @@ void mainboard_get_dxio_ddi_descriptors(
 			crater_ddi_descriptors[1].connector_type = DDI_HDMI;
 	}
 
+	static const fsp_dxio_descriptor crater_dxio_descriptors[] = {
+		mxm_dxio_descriptor,
+		ssd_dxio_descriptor
+	};
+
 	*dxio_descs = crater_dxio_descriptors;
 	*dxio_num = ARRAY_SIZE(crater_dxio_descriptors);
 	*ddi_descs = crater_ddi_descriptors;