arm64: tegra132: tegra210: Remove old arm64/stage_entry.S
This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Julius Werner
parent
d3634c108d
commit
7dcf9d51e5
33 changed files with 126 additions and 440 deletions
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@ -17,11 +17,6 @@ config SOC_NVIDIA_TEGRA132
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if SOC_NVIDIA_TEGRA132
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# TODO: Remove after replacing arch/arm64/stage_entry.S
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config STACK_SIZE
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hex
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default 0x1000
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config MAINBOARD_DO_DSI_INIT
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bool "Use dsi graphics interface"
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depends on MAINBOARD_DO_NATIVE_VGA_INIT
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@ -36,10 +31,6 @@ config MAINBOARD_DO_SOR_INIT
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help
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Initialize dp display
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config MAX_CPUS
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int
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default 2
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config MTS_DIRECTORY
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string "Directory where MTS microcode files are located"
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default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod"
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@ -90,6 +90,7 @@ ramstage-y += ramstage.c
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ramstage-y += mmu_operations.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += ../tegra/usb.c
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ramstage-y += stage_entry.S
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modules_arm-y += monotonic_timer.c
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@ -14,6 +14,7 @@
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*/
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#include <memlayout.h>
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#include <rules.h>
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#include <arch/header.ld>
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@ -29,7 +30,11 @@ SECTIONS
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SRAM_START(0x40000000)
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PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
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PRERAM_CBFS_CACHE(0x40002000, 84K)
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STACK(0x40017000, 14K)
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#if ENV_ARM64
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STACK(0x40017000, 8K)
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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STACK(0x40019000, 6K)
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#endif
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TIMESTAMP(0x4001A800, 2K)
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BOOTBLOCK(0x4001B800, 22K)
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ROMSTAGE(0x40021000, 124K)
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@ -14,6 +14,7 @@
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*/
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#include <memlayout.h>
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#include <rules.h>
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#include <arch/header.ld>
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@ -29,8 +30,12 @@ SECTIONS
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SRAM_START(0x40000000)
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PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
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PRERAM_CBFS_CACHE(0x40002000, 72K)
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VBOOT2_WORK(0x40014000, 16K)
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STACK(0x40018000, 2K)
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VBOOT2_WORK(0x40014000, 12K)
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#if ENV_ARM64
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STACK(0x40017000, 3K)
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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STACK(0x40017C00, 3K)
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#endif
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TIMESTAMP(0x40018800, 2K)
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BOOTBLOCK(0x40019000, 22K)
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VERSTAGE(0x4001e800, 55K)
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@ -1,55 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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ENTRY(maincpu_setup)
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/*
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* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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*/
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msr cpsr, #0xdf
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ldr sp, maincpu_stack_pointer
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eor lr, lr
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ldr r0, maincpu_entry_point
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bx r0
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ENDPROC(maincpu_setup)
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.align 2
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.global maincpu_stack_pointer
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maincpu_stack_pointer:
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.word 0
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.global maincpu_entry_point
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maincpu_entry_point:
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.word 0
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@ -14,6 +14,7 @@
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*/
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#include <arch/stages.h>
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#include <gic.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/mc.h>
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@ -28,8 +29,14 @@ static void lock_down_vpr(void)
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write32(®s->video_protect_reg_ctrl, 1);
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}
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void arm64_soc_init(void)
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/* Tegra-specific entry point, called from assembly in stage_entry.S */
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void ramstage_entry(void);
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void ramstage_entry(void)
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{
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/* TODO: Is this still needed? */
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gic_init();
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/* TODO: Move TrustZone setup to BL31? */
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trustzone_region_init();
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tegra132_mmu_init();
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@ -40,4 +47,7 @@ void arm64_soc_init(void)
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/* Lock down VPR */
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lock_down_vpr();
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/* Jump to boot state machine in common code. */
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main();
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}
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@ -19,6 +19,7 @@
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#include <cbmem.h>
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#include <console/cbmem_console.h>
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#include <console/console.h>
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#include <lib.h>
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#include <program_loading.h>
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#include <soc/addressmap.h>
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#include <soc/ccplex.h>
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@ -26,6 +27,7 @@
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#include <soc/sdram.h>
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#include <soc/sdram_configs.h>
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#include <soc/romstage.h>
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#include <symbols.h>
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#include <timer.h>
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#include <timestamp.h>
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@ -82,6 +84,9 @@ void romstage(void)
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void platform_prog_run(struct prog *prog)
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{
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/* We'll switch to a new stack, so validate our old one here. */
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checkstack(_estack, 0);
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ccplex_cpu_start(prog_entry(prog));
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clock_halt_avp();
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24
src/soc/nvidia/tegra132/stage_entry.S
Normal file
24
src/soc/nvidia/tegra132/stage_entry.S
Normal file
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/asm.h>
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ENTRY(stage_entry)
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/* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */
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bl arm64_init_cpu
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/* Jump to Tegra-specific C entry point. */
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bl ramstage_entry
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ENDPROC(stage_entry)
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@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210
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select ARCH_VERSTAGE_ARMV4
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select ARCH_ROMSTAGE_ARMV4
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select ARCH_RAMSTAGE_ARMV8_64
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select ARCH_ARM64_CPU_CORTEX_A57
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select BOOTBLOCK_CONSOLE
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select GIC
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select HAVE_MONOTONIC_TIMER
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@ -22,11 +21,6 @@ if SOC_NVIDIA_TEGRA210
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config CHROMEOS
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select CHROMEOS_RAMOOPS_NON_ACPI
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# TODO: Remove after replacing arch/arm64/stage_entry.S
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config STACK_SIZE
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hex
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default 0x1000
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config MAINBOARD_DO_DSI_INIT
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bool "Use dsi graphics interface"
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depends on MAINBOARD_DO_NATIVE_VGA_INIT
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@ -41,10 +35,6 @@ config MAINBOARD_DO_SOR_INIT
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help
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Initialize dp display
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config MAX_CPUS
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int
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default 4
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choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES
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prompt "Serial Console UART"
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default CONSOLE_SERIAL_TEGRA210_UARTA
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@ -23,7 +23,7 @@
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static void enable_core_clocks(int cpu)
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{
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const uint32_t cpu_clocks[CONFIG_MAX_CPUS] = {
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const uint32_t cpu_clocks[] = {
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[0] = CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_DBG0 |
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CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CX0,
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[1] = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 |
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@ -14,6 +14,7 @@
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*/
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#include <memlayout.h>
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#include <rules.h>
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#include <arch/header.ld>
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@ -29,7 +30,11 @@ SECTIONS
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SRAM_START(0x40000000)
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PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
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PRERAM_CBFS_CACHE(0x40002000, 84K)
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STACK(0x40017000, 16K)
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#if ENV_ARM64
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STACK(0x40017000, 8K)
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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STACK(0x40019000, 8K)
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#endif
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TIMESTAMP(0x4001B000, 2K)
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BOOTBLOCK(0x4001B800, 24K)
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ROMSTAGE(0x40022000, 120K)
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@ -14,6 +14,7 @@
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*/
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#include <memlayout.h>
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#include <rules.h>
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#include <arch/header.ld>
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@ -29,8 +30,12 @@ SECTIONS
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SRAM_START(0x40000000)
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PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
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PRERAM_CBFS_CACHE(0x40002000, 36K)
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VBOOT2_WORK(0x4000B000, 16K)
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STACK(0x4000F000, 2K)
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VBOOT2_WORK(0x4000B000, 12K)
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#if ENV_ARM64
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STACK(0x4000E000, 3K)
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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STACK(0x4000EC00, 3K)
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#endif
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TIMESTAMP(0x4000F800, 2K)
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BOOTBLOCK(0x40010000, 28K)
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VERSTAGE(0x40017000, 64K)
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@ -1,55 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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ENTRY(maincpu_setup)
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/*
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* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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*/
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msr cpsr, #0xdf
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ldr sp, maincpu_stack_pointer
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eor lr, lr
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ldr r0, maincpu_entry_point
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bx r0
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ENDPROC(maincpu_setup)
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.align 2
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.global maincpu_stack_pointer
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maincpu_stack_pointer:
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.word 0
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.global maincpu_entry_point
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maincpu_entry_point:
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.word 0
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@ -16,12 +16,13 @@
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#include <arch/clock.h>
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#include <arch/cpu.h>
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#include <arch/stages.h>
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#include <gic.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/mmu_operations.h>
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#include <soc/mtc.h>
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void arm64_arch_timer_init(void)
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static void arm64_arch_timer_init(void)
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{
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uint32_t freq = clock_get_osc_khz() * 1000;
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// Set the cntfrq register.
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@ -47,11 +48,20 @@ static void mselect_enable_wrap(void)
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write32((void *)TEGRA_MSELECT_CONFIG, reg);
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}
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void arm64_soc_init(void)
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/* Tegra-specific entry point, called from assembly in stage_entry.S */
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void ramstage_entry(void);
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void ramstage_entry(void)
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{
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/* TODO: Is this still needed? */
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gic_init();
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/* TODO: Move arch timer setup to BL31? */
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arm64_arch_timer_init();
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/* Enable WRAP to INCR burst type conversion in MSELECT */
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mselect_enable_wrap();
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/* TODO: Move TrustZone setup to BL31? */
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trustzone_region_init();
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tegra210_mmu_init();
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@ -60,4 +70,7 @@ void arm64_soc_init(void)
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if (tegra210_run_mtc() != 0)
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printk(BIOS_ERR, "MTC: No training data.\n");
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/* Jump to boot state machine in common code. */
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main();
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}
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@ -19,6 +19,7 @@
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#include <cbmem.h>
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#include <console/cbmem_console.h>
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#include <console/console.h>
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#include <lib.h>
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#include <program_loading.h>
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#include <soc/addressmap.h>
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#include <soc/ccplex.h>
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@ -27,6 +28,7 @@
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#include <soc/sdram_configs.h>
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#include <soc/romstage.h>
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#include <soc/nvidia/tegra/apbmisc.h>
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#include <symbols.h>
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#include <timer.h>
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#include <timestamp.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@ -86,6 +88,9 @@ void romstage(void)
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void platform_prog_run(struct prog *prog)
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{
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/* We'll switch to a new stack, so validate our old one here. */
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checkstack(_estack, 0);
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ccplex_cpu_start(prog_entry(prog));
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clock_halt_avp();
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@ -82,10 +82,10 @@
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ENTRY(stage_entry)
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t210_a57_fixup
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b arm64_cpu_startup
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ENDPROC(stage_entry)
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ENTRY(tegra210_reset_handler)
|
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t210_a57_fixup
|
||||
b arm64_cpu_startup_resume
|
||||
ENDPROC(tegra210_reset_handler)
|
||||
/* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */
|
||||
bl arm64_init_cpu
|
||||
|
||||
/* Jump to Tegra-specific C entry point. */
|
||||
bl ramstage_entry
|
||||
ENDPROC(stage_entry)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue