From 7da36ad79adb2f9f85b2780402c6a137f9dc71a6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 21 Mar 2025 18:39:04 +0530 Subject: [PATCH] mb/google/bluey: Add initial support for Bluey This commit introduces basic support for the google/bluey mainboard, based on the Qualcomm X1P-42-100 SoC. Changes: - Add placeholder mainboard callbacks to enable control flow from /lib and Qualcomm SoC code. - Populate the bluey mainboard directory with a copy of the herobrine codebase, removing SoC/mainboard-specific implementations. This provides a minimal working build for google/bluey, allowing upstream builders to compile the mainboard. This facilitates easier verification of subsequent changes. BUG=b:404985109 TEST=Successfully built google/bluey with Qualcomm X1P-42-100 SoC. Change-Id: Id0da1846b8aef6f4ef4345be9cd803aa60406cdf Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/86973 Reviewed-by: Kapil Porwal Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/bluey/Kconfig | 61 +++++++++++++++++++++++ src/mainboard/google/bluey/Kconfig.name | 6 +++ src/mainboard/google/bluey/Makefile.mk | 11 ++++ src/mainboard/google/bluey/board.h | 14 ++++++ src/mainboard/google/bluey/board_info.txt | 6 +++ src/mainboard/google/bluey/boardid.c | 17 +++++++ src/mainboard/google/bluey/bootblock.c | 8 +++ src/mainboard/google/bluey/chromeos.c | 31 ++++++++++++ src/mainboard/google/bluey/chromeos.fmd | 42 ++++++++++++++++ src/mainboard/google/bluey/devicetree.cb | 7 +++ src/mainboard/google/bluey/mainboard.c | 24 +++++++++ src/mainboard/google/bluey/reset.c | 11 ++++ src/mainboard/google/bluey/romstage.c | 8 +++ 13 files changed, 246 insertions(+) create mode 100644 src/mainboard/google/bluey/Kconfig create mode 100644 src/mainboard/google/bluey/Kconfig.name create mode 100644 src/mainboard/google/bluey/Makefile.mk create mode 100644 src/mainboard/google/bluey/board.h create mode 100644 src/mainboard/google/bluey/board_info.txt create mode 100644 src/mainboard/google/bluey/boardid.c create mode 100644 src/mainboard/google/bluey/bootblock.c create mode 100644 src/mainboard/google/bluey/chromeos.c create mode 100644 src/mainboard/google/bluey/chromeos.fmd create mode 100644 src/mainboard/google/bluey/devicetree.cb create mode 100644 src/mainboard/google/bluey/mainboard.c create mode 100644 src/mainboard/google/bluey/reset.c create mode 100644 src/mainboard/google/bluey/romstage.c diff --git a/src/mainboard/google/bluey/Kconfig b/src/mainboard/google/bluey/Kconfig new file mode 100644 index 0000000000..a22cae6bab --- /dev/null +++ b/src/mainboard/google/bluey/Kconfig @@ -0,0 +1,61 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_GOOGLE_BLUEY_COMMON + def_bool n + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select I2C_TPM + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_TPM2 + select RTC + select SOC_QUALCOMM_X1P42100 + select SPI_FLASH + select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_MACRONIX + select SPI_FLASH_WINBOND + select TPM_GOOGLE_TI50 + +config BOARD_GOOGLE_BASEBOARD_BLUEY + def_bool n + select BOARD_GOOGLE_BLUEY_COMMON + +config BOARD_GOOGLE_BLUEY + select BOARD_GOOGLE_BASEBOARD_BLUEY + +if BOARD_GOOGLE_BLUEY_COMMON + +config MAINBOARD_DIR + default "google/bluey" + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + default "Bluey" if BOARD_GOOGLE_BLUEY + +config DRIVER_TPM_I2C_BUS + depends on I2C_TPM + hex + default 0x00 # TODO + +config DRIVER_TPM_I2C_ADDR + default 0x50 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x0 # TODO + +endif # BOARD_GOOGLE_BLUEY_COMMON diff --git a/src/mainboard/google/bluey/Kconfig.name b/src/mainboard/google/bluey/Kconfig.name new file mode 100644 index 0000000000..19cb4b1e17 --- /dev/null +++ b/src/mainboard/google/bluey/Kconfig.name @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +comment "Bluey" + +config BOARD_GOOGLE_BLUEY + bool "-> Bluey" diff --git a/src/mainboard/google/bluey/Makefile.mk b/src/mainboard/google/bluey/Makefile.mk new file mode 100644 index 0000000000..553634c29c --- /dev/null +++ b/src/mainboard/google/bluey/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all-y += boardid.c +all-y += chromeos.c +all-y += reset.c + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/bluey/board.h b/src/mainboard/google/bluey/board.h new file mode 100644 index 0000000000..e6de22ef48 --- /dev/null +++ b/src/mainboard/google/bluey/board.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GOOGLE_BLUEY_BOARD_H +#define MAINBOARD_GOOGLE_BLUEY_BOARD_H + +#include +#include + +#define GPIO_AP_EC_INT GPIO(0) +#define GPIO_GSC_AP_INT GPIO(0) + +void setup_chromeos_gpios(void); + +#endif /* MAINBOARD_GOOGLE_BLUEY_BOARD_H */ diff --git a/src/mainboard/google/bluey/board_info.txt b/src/mainboard/google/bluey/board_info.txt new file mode 100644 index 0000000000..be67b9c6af --- /dev/null +++ b/src/mainboard/google/bluey/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Bluey Qualcomm X1P-42-100 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/bluey/boardid.c b/src/mainboard/google/bluey/boardid.c new file mode 100644 index 0000000000..b529ff1ec1 --- /dev/null +++ b/src/mainboard/google/bluey/boardid.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + /* Placeholder */ + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + /* Placeholder */ + return id; +} diff --git a/src/mainboard/google/bluey/bootblock.c b/src/mainboard/google/bluey/bootblock.c new file mode 100644 index 0000000000..b8edccd598 --- /dev/null +++ b/src/mainboard/google/bluey/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void bootblock_mainboard_init(void) +{ + /* Placeholder */ +} diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c new file mode 100644 index 0000000000..aad0b0fea3 --- /dev/null +++ b/src/mainboard/google/bluey/chromeos.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "board.h" +#include + +void setup_chromeos_gpios(void) +{ + gpio_input_pullup(GPIO_AP_EC_INT); + + gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + /* TODO: Add required GPIO after referring to the schematics */ + const struct lb_gpio chromeos_gpios[] = { + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, + {GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT), + "TPM interrupt"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int cr50_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_GSC_AP_INT); +} diff --git a/src/mainboard/google/bluey/chromeos.fmd b/src/mainboard/google/bluey/chromeos.fmd new file mode 100644 index 0000000000..0ad818b6db --- /dev/null +++ b/src/mainboard/google/bluey/chromeos.fmd @@ -0,0 +1,42 @@ +## SPDX-License-Identifier: GPL-2.0-only + +FLASH@0x0 CONFIG_ROM_SIZE { + WP_RO 4M { + RO_SECTION 0x3c4000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + FMAP@0x3c0000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 + } + RO_GSCVD 8K + RO_VPD(PRESERVE) + } + + RW_MISC 128K { + UNIFIED_MRC_CACHE(PRESERVE) 64K { + RECOVERY_MRC_CACHE 32K + RW_MRC_CACHE 32K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + } + + RW_SECTION_A 1536K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + RW_SECTION_B 1536K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) +} diff --git a/src/mainboard/google/bluey/devicetree.cb b/src/mainboard/google/bluey/devicetree.cb new file mode 100644 index 0000000000..7aed490a72 --- /dev/null +++ b/src/mainboard/google/bluey/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/qualcomm/x1p42100 + device cpu_cluster 0 on end + device domain 0 on + end +end diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c new file mode 100644 index 0000000000..c633e8dfb1 --- /dev/null +++ b/src/mainboard/google/bluey/mainboard.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +bool mainboard_needs_pcie_init(void) +{ + /* Placeholder */ + return false; +} + +static void mainboard_init(struct device *dev) +{ + /* Placeholder */ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/bluey/reset.c b/src/mainboard/google/bluey/reset.c new file mode 100644 index 0000000000..d64c650b99 --- /dev/null +++ b/src/mainboard/google/bluey/reset.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) +{ + google_chromeec_reboot(EC_REBOOT_COLD, 0); +} diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c new file mode 100644 index 0000000000..8d15157e70 --- /dev/null +++ b/src/mainboard/google/bluey/romstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void platform_romstage_main(void) +{ + /* Placeholder */ +}