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haswell: add option to change DqPinsInterleaved

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Some mainboards will need to have this set.

BUG=none
BRANCH=none
TEST=Boot coreboot on Falco with no visible changes
     (Similar change to coreboot required)
Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
Reviewed-on: https://gerrit.chromium.org/gerrit/65722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
This commit is contained in:
Stefan Reinauer 2013-08-13 11:18:42 -07:00 • committed by ChromeBot
commit 7d0edf607e
1 changed files with 2 additions and 1 deletions
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3
src/northbridge/intel/haswell/pei_data.h
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@ -31,7 +31,7 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 14
#define PEI_VERSION 15
#define MAX_USB2_PORTS 16
#define MAX_USB3_PORTS 16
@ -92,6 +92,7 @@ struct pei_data
int dimm_channel1_disabled;
/* Enable 2x Refresh Mode */
int ddr_refresh_2x;
int dq_pins_interleaved;
/* Data read from flash and passed into MRC */
unsigned char *mrc_input;
unsigned int mrc_input_len;