From 7b28e9e8ff7abe89bcb51089f2b1425374e2a2b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Wed, 12 Oct 2016 00:18:02 +0200 Subject: [PATCH] UPSTREAM: arch/riscv: In trap handler, don't print SP twice The stack pointer (SP) is already printed in print_trap_information. Don't print it again in handle_misaligned_{load,store}. BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer Reviewed-on: https://review.coreboot.org/16996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2 Reviewed-on: https://chromium-review.googlesource.com/400463 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/arch/riscv/trap_handler.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 59aa2214bc..ad4992803c 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -173,7 +173,6 @@ static uint32_t fetch_instruction(uintptr_t vaddr) { void handle_misaligned_load(trapframe *tf) { printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); - printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); uintptr_t faultingInstructionAddr = tf->epc; insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr); printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); @@ -203,7 +202,6 @@ void handle_misaligned_load(trapframe *tf) { void handle_misaligned_store(trapframe *tf) { printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); - printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); uintptr_t faultingInstructionAddr = tf->epc; insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr); printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);