diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c
index 24c7cc59e9..84fb16347d 100644
--- a/src/soc/mediatek/mt8189/pll.c
+++ b/src/soc/mediatek/mt8189/pll.c
@@ -66,7 +66,9 @@ enum mux_id {
 	CLK_TOP_AUDIO_H_SEL,
 	CLK_TOP_MCUPM_SEL,
 	CLK_TOP_MEM_SUB_SEL,
+	CLK_TOP_MEM_SUB_PERI_SEL,
 	CLK_TOP_MEM_SUB_U_SEL,
+	CLK_TOP_EMI_N_SEL,
 	CLK_TOP_DXCC_SEL,
 	CLK_TOP_DP_SEL,
 	CLK_TOP_EDP_SEL,
@@ -192,7 +194,9 @@ static const struct mux muxes[] = {
 	CKSYS_MUX_UPD(CLK_TOP_AUDIO_H_SEL, clk_cfg[12], 8, 2, clk_cfg_update[1], 18),
 	CKSYS_MUX_UPD(CLK_TOP_MCUPM_SEL, clk_cfg[12], 16, 2, clk_cfg_update[1], 19),
 	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_SEL, clk_cfg[12], 24, 4, clk_cfg_update[1], 20),
+	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_PERI_SEL, clk_cfg[13], 0, 3, clk_cfg_update[1], 21),
 	CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_U_SEL, clk_cfg[13], 8, 3, clk_cfg_update[1], 22),
+	CKSYS_MUX_UPD(CLK_TOP_EMI_N_SEL, clk_cfg[13], 16, 3, clk_cfg_update[1], 23),
 	CKSYS_MUX_UPD(CLK_TOP_DXCC_SEL, clk_cfg[15], 24, 2, clk_cfg_update[2], 1),
 	CKSYS_MUX_UPD(CLK_TOP_DP_SEL, clk_cfg[16], 16, 3, clk_cfg_update[2], 4),
 	CKSYS_MUX_UPD(CLK_TOP_EDP_SEL, clk_cfg[16], 24, 3, clk_cfg_update[2], 5),
@@ -250,7 +254,9 @@ static const struct mux_sel mux_sels[] = {
 	{ .id = CLK_TOP_AUDIO_H_SEL, .sel = 3 },
 	{ .id = CLK_TOP_MCUPM_SEL, .sel = 2 },
 	{ .id = CLK_TOP_MEM_SUB_SEL, .sel = 9 },
+	{ .id = CLK_TOP_MEM_SUB_PERI_SEL, .sel = 7 },
 	{ .id = CLK_TOP_MEM_SUB_U_SEL, .sel = 7 },
+	{ .id = CLK_TOP_EMI_N_SEL, .sel = 2 },
 	{ .id = CLK_TOP_DXCC_SEL, .sel = 1 },
 	{ .id = CLK_TOP_DP_SEL, .sel = 4 },
 	{ .id = CLK_TOP_EDP_SEL, .sel = 4 },