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mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked

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With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.

BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
     test reboot 30 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Casper Chang 2022-03-01 13:13:20 +08:00 • committed by Subrata Banik
commit 7a7a533725
2 changed files with 6 additions and 2 deletions
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4
src/mainboard/google/brya/variants/primus/gpio.c
View file

@ -23,7 +23,7 @@ static const struct pad_config override_gpio_table[] = {
/* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
PAD_CFG_GPO(GPP_B3, 1, DEEP),
/* B15 : TIME_SYNC0 ==> NC */
PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
@ -88,6 +88,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 0, DEEP),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */

4
src/mainboard/google/brya/variants/primus4es/gpio.c
View file

@ -23,7 +23,7 @@ static const struct pad_config override_gpio_table[] = {
/* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
PAD_CFG_GPO(GPP_B3, 1, DEEP),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
@ -88,6 +88,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 0, DEEP),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */