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UPSTREAM: arch/riscv: Remove enter_supervisor

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This function is unused since coreboot starts payloads in machine mode,
and it uses the obsolete eret instruction.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15729
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I98d7d0de5a3959821c21a0ba4319efb610fdefde
Reviewed-on: https://chromium-review.googlesource.com/361643
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2016-07-18 17:56:59 +02:00 • committed by chrome-bot
commit 7a6eb8b178
2 changed files with 0 additions and 6 deletions
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1
src/arch/riscv/include/vm.h
View file

@ -57,7 +57,6 @@
typedef uintptr_t pte_t;
extern pte_t* root_page_table;
void enter_supervisor(void);
void initVirtualMemory(void);
size_t pte_ppn(pte_t pte);

5
src/arch/riscv/virtual_memory.c
View file

@ -29,11 +29,6 @@ void walk_page_table(void) {
printk(BIOS_DEBUG, "root_page_table: %p\n", t);
}
void enter_supervisor(void) {
// enter supervisor mode
asm volatile("la t0, 1f; csrw mepc, t0; eret; 1:" ::: "t0");
}
void flush_tlb(void)
{
asm volatile("sfence.vm");