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Moved MPC7410 initialzation code to pmc/altimus/mpc7410.

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This commit is contained in:
Greg Watson 2003-06-09 17:36:24 +00:00
commit 7a52a73fbc
1 changed files with 6 additions and 181 deletions
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187
src/arch/ppc/config/crt0.base
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@ -6,11 +6,6 @@
#include "ppcreg.h"
#include <ppc_asm.tmpl>
#define BSP_IOREGION1 0x80000000
#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#define BSP_IOREGION2 0xFD000000
#define BSP_IOMASK2 BAT_BL_32M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
@ -33,162 +28,10 @@ _start:
.space (0x3000)
system_reset:
isync
/*
* Disable dcache and MMU, so that init_memory stands a chance
*/
li r0, 0
sync
mtspr HID0, r0
sync
mtmsr r0
isync
/*
* Invalidate BATS
*/
mtibatu 0, r0
mtibatu 1, r0
mtibatu 2, r0
mtibatu 3, r0
isync
mtdbatu 0, r0
mtdbatu 1, r0
mtdbatu 2, r0
mtdbatu 3, r0
isync
/*
* Clear segment registers
*/
mtsr 0, r0
isync
mtsr 1, r0
isync
mtsr 2, r0
isync
mtsr 3, r0
isync
mtsr 4, r0
isync
mtsr 5, r0
isync
mtsr 6, r0
isync
mtsr 7, r0
isync
mtsr 8, r0
isync
mtsr 9, r0
isync
mtsr 10, r0
isync
mtsr 11, r0
isync
mtsr 12, r0
isync
mtsr 13, r0
isync
mtsr 14, r0
isync
mtsr 15, r0
isync
/*
* Initialize northbridge. This has to happen early because it
* resets memory. Memory is on at this point, albeit with
* pessimistic settings. We reconfigure later using I2C.
*/
bl bsp_init_northbridge
/*
* CACHE_RAM_BASE - this is a 128KB BAT covering the
* __start_data address. We allocate it in the cache so
* that we can continue running and
* report a memory failure in early startup code.
*/
/*
* Set up DBATs
*/
//lis r2, CACHE_RAM_BASE@ha
//lis r2, _RAMBASE@ha
//ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
//ori r2, r2, BAT_READ_WRITE
lis r2, 0@ha
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE
mtdbatu 0, r3
mtdbatl 0, r2
isync
//lis r2, _ROMBASE@ha
//ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
//ori r2, r2, BAT_READ_ONLY
//mtdbatu 1, r3
//mtdbatl 1, r2
lis r2, 0xfc000000@ha
ori r3, r2, BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 1, r3
mtdbatl 1, r2
isync
lis r2, BSP_IOREGION1@h
ori r3, r2, BSP_IOMASK1
ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
mtdbatu 2, r3
mtdbatl 2, r2
isync
//lis r2, BSP_IOREGION2@h
//ori r3, r2, BSP_IOMASK2
//ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
//mtdbatu 3, r3
//mtdbatl 3, r2
/*
* IBATS
*/
lis r2, 0@ha
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_WRITE
mtibatu 0, r3
mtibatl 0, r2
isync
lis r2, _ROMBASE@ha
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
ori r2, r2, BAT_READ_ONLY
mtibatu 1, r3
mtibatl 1, r2
isync
/*
* Invalidate tlb entries
*/
lis r3, 0
lis r5, 0x4
isync
tlblp:
tlbie r3
sync
addi r3, r3, 0x1000
cmp 0, 0, r3, r5
blt tlblp
sync
/*
* Enable MMU
*/
mfmsr r2
ori r2, r2, MSR_DR | MSR_IR
isync
mtmsr r2
isync
#include "crt0_includes.h"
start_payload:
/*
* Relocate payload (text & data) to ram
*/
@ -201,39 +44,21 @@ tlblp:
* Skip if they're the same
*/
cmp 0, 0, r3, r4
beq skip
beq 1f
lis r7, _eliseg@ha
addi r7, r7, _eliseg@l
relocate_loop:
2:
lwzx r5, 0, r3
stwx r5, 0, r4
addi r3, r3, 4
addi r4, r4, 4
cmp 0, 0, r3, r7
ble relocate_loop
skip:
/*
* Enable L1 dcache
*/
mfspr r2, HID0
ori r2, r2, HID0_DCE | HID0_DCFI
sync
mtspr HID0, r2
/*
* Enable L1 icache
*/
mfspr r2, HID0
ori r2, r2, HID0_ICE | HID0_ICFI
isync
mtspr HID0, r2
ble 2b
1:
/*
* Start payload
*/
b _iseg
#include "crt0_includes.h"