cbmem_top_chipset: Change the return value to uintptr_t

Get rid of a lot of casts.

Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>

src/soc/amd/stoneyridge/memmap.c

@@ -12,7 +12,7 @@
 #include <soc/iomap.h>
 #include <amdblocks/biosram.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	msr_t tom = rdmsr(TOP_MEM);
 
@@ -20,8 +20,7 @@ void *cbmem_top_chipset(void)
 		return 0;
 
 	/* 8MB alignment to keep MTRR usage low */
-	return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
-				  - CONFIG_SMM_TSEG_SIZE, 8 * MiB);
+	return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE, 8 * MiB);
 }
 
 static uintptr_t smm_region_start(void)

src/soc/cavium/cn81xx/cbmem.c

@@ -5,8 +5,8 @@
 #include <soc/sdram.h>
 #include <symbols.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	/* Make sure not to overlap with reserved ATF scratchpad */
-	return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB);
+	return (uintptr_t)_dram + (sdram_size_mb() - 1) * MiB;
 }

src/soc/intel/baytrail/memmap.c

@@ -16,9 +16,9 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *) smm_region_start();
+	return smm_region_start();
 }
 
 void smm_region(uintptr_t *start, size_t *size)

src/soc/intel/braswell/memmap.c

@@ -19,7 +19,7 @@ void smm_region(uintptr_t *start, size_t *size)
 	*size = smm_region_size();
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	uintptr_t smm_base;
 	size_t smm_size;
@@ -53,5 +53,5 @@ void *cbmem_top_chipset(void)
 	*/
 
 	smm_region(&smm_base, &smm_size);
-	return (void *)smm_base;
+	return smm_base;
 }

src/soc/intel/broadwell/memmap.c

@@ -29,9 +29,9 @@ static uintptr_t dpr_region_start(void)
 	return tom;
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *) dpr_region_start();
+	return dpr_region_start();
 }
 
 void smm_region(uintptr_t *start, size_t *size)

src/soc/mediatek/common/cbmem.c

@@ -7,7 +7,7 @@
 
 #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
+	return MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
 }

src/soc/nvidia/tegra124/cbmem.c

@@ -1,10 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <cbmem.h>
+#include <commonlib/bsd/helpers.h>
 #include <soc/display.h>
 #include <soc/sdram.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL);
+	return (sdram_max_addressable_mb() - FB_SIZE_MB) * MiB;
 }

src/soc/nvidia/tegra210/cbmem.c

@@ -3,7 +3,7 @@
 #include <cbmem.h>
 #include <soc/addressmap.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	static uintptr_t addr;
 
@@ -19,5 +19,5 @@ void *cbmem_top_chipset(void)
 			addr = end_mib << 20;
 	}
 
-	return (void *)addr;
+	return addr;
 }

src/soc/nvidia/tegra210/ramstage.c

@@ -59,7 +59,7 @@ void ramstage_entry(void)
 	/* Ramstage is run on a different core, so passing cbmem_top
 	   via calling arguments is not an option, but it is not a problem
 	   to call cbmem_top_chipset() again here to populate _cbmem_top_ptr. */
-	_cbmem_top_ptr = (uintptr_t)cbmem_top_chipset();
+	_cbmem_top_ptr = cbmem_top_chipset();
 
 	/* Jump to boot state machine in common code. */
 	main();

src/soc/qualcomm/ipq40xx/cbmem.c

@@ -10,7 +10,7 @@ void ipq_cbmem_backing_store_ready(void)
 	cbmem_backing_store_ready = 1;
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	/*
 	 * In romstage, make sure that cbmem backing store is ready before
@@ -19,7 +19,7 @@ void *cbmem_top_chipset(void)
 	 * for loading ipq blobs before DRAM is initialized).
 	 */
 	if (cbmem_backing_store_ready == 0)
-		return NULL;
+		return 0;
 
-	return _memlayout_cbmem_top;
+	return (uintptr_t)_memlayout_cbmem_top;
 }

src/soc/qualcomm/ipq806x/cbmem.c

@@ -10,7 +10,7 @@ void ipq_cbmem_backing_store_ready(void)
 	cbmem_backing_store_ready = 1;
 }
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
 	/*
 	 * In romstage, make sure that cbmem backing store is ready before
@@ -20,7 +20,7 @@ void *cbmem_top_chipset(void)
 	 * initialized).
 	 */
 	if (cbmem_backing_store_ready == 0)
-		return NULL;
+		return 0;
 
-	return _memlayout_cbmem_top;
+	return (uintptr_t)_memlayout_cbmem_top;
 }

src/soc/qualcomm/qcs405/cbmem.c

@@ -2,7 +2,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)((uintptr_t)3 * GiB);
+	return (uintptr_t)3 * GiB;
 }

src/soc/qualcomm/sc7180/cbmem.c

@@ -2,7 +2,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)((uintptr_t)4 * GiB);
+	return (uintptr_t)4 * GiB;
 }

src/soc/qualcomm/sc7280/cbmem.c

@@ -2,7 +2,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)((uintptr_t)4 * GiB);
+	return (uintptr_t)4 * GiB;
 }

src/soc/rockchip/common/cbmem.c

@@ -6,8 +6,7 @@
 #include <soc/sdram.h>
 #include <symbols.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB,
-			   MAX_DRAM_ADDRESS);
+	return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS);
 }

src/soc/samsung/exynos5250/cbmem.c

@@ -3,7 +3,7 @@
 #include <cbmem.h>
 #include <soc/cpu.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)(get_fb_base_kb() * KiB);
+	return get_fb_base_kb() * KiB;
 }

src/soc/samsung/exynos5420/cbmem.c

@@ -3,7 +3,7 @@
 #include <cbmem.h>
 #include <soc/cpu.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)(get_fb_base_kb() * KiB);
+	return get_fb_base_kb() * KiB;
 }

src/soc/sifive/fu540/cbmem.c

@@ -6,8 +6,7 @@
 #include <soc/sdram.h>
 #include <symbols.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB,
-			   FU540_MAXDRAM);
+	return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM);
 }

src/soc/ti/am335x/cbmem.c

@@ -4,7 +4,7 @@
 #include <commonlib/bsd/helpers.h>
 #include <symbols.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return _dram + CONFIG_DRAM_SIZE_MB * MiB;
+	return (uintptr_t)_dram + CONFIG_DRAM_SIZE_MB * MiB;
 }

src/soc/ucb/riscv/cbmem.c

@@ -4,7 +4,7 @@
 #include <symbols.h>
 #include <ramdetect.h>
 
-void *cbmem_top_chipset(void)
+uintptr_t cbmem_top_chipset(void)
 {
-	return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
+	return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
 }