From 7946d2d65dba34f9e7bcf76e18b6e2193994c889 Mon Sep 17 00:00:00 2001 From: Tongtong Pan Date: Thu, 6 Nov 2025 10:31:40 +0800 Subject: [PATCH] mb/google/fatcat/var/felino: Add reset_gpio for SSD RTD3 configuration To resolve the issue of probabilistic inability to enter s0ix, We need to 1.Add reset_gpio for SSD RTD3 configuration 2.Disable card reader in coreboot Regarding adding reset_gpio for SSD RTD3 configuration The PCIE SSD PERST part is added in the schematic diagram of the V4 version, So GPP_F20 needs to be configured on felino, and keeps NC on felino4es. BUG=b:431653999 TEST=dut can successfully enter S0IX during stress test. Change-Id: I7dbb8b167fd7d519cd8c148ff7ead328c8c11d81 Signed-off-by: Tongtong Pan Reviewed-on: https://review.coreboot.org/c/coreboot/+/89927 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Pranava Y N --- src/mainboard/google/fatcat/variants/felino/gpio.c | 7 ++++++- .../google/fatcat/variants/felino/overridetree.cb | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index 3a82f97155..45e2ad4670 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -288,8 +288,13 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F18, NONE), /* GPP_F19: GPP_F19 */ PAD_NC(GPP_F19, NONE), - /* GPP_F20: NC */ +#if CONFIG(BOARD_GOOGLE_FELINO4ES) + /* GPP_F20: Not used */ PAD_NC(GPP_F20, NONE), +#else + /* GPP_F20: SOC_SSD1_RST# */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), +#endif /* GPP_F22: NC */ PAD_NC(GPP_F22, NONE), /* GPP_F23: NC */ diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index b4869ead78..0d2b9c2da8 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -252,6 +252,7 @@ device ref tbt_pcie_rp0 on end chip soc/intel/common/block/pcie/rtd3 register "is_storage" = "true" register "srcclk_pin" = "0" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" device generic 0 on end end end # Gen5 SSD