diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 3a82f97155..45e2ad4670 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -288,8 +288,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F18, NONE),
 	/* GPP_F19:     GPP_F19 */
 	PAD_NC(GPP_F19, NONE),
-	/* GPP_F20:     NC */
+#if CONFIG(BOARD_GOOGLE_FELINO4ES)
+	/* GPP_F20:     Not used */
 	PAD_NC(GPP_F20, NONE),
+#else
+	/* GPP_F20:     SOC_SSD1_RST# */
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
+#endif
 	/* GPP_F22:     NC */
 	PAD_NC(GPP_F22, NONE),
 	/* GPP_F23:     NC */
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index b4869ead78..0d2b9c2da8 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -252,6 +252,7 @@ device ref tbt_pcie_rp0 on end
 			chip soc/intel/common/block/pcie/rtd3
 				register "is_storage" = "true"
 				register "srcclk_pin" = "0"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
 				device generic 0 on end
 			end
 		end # Gen5 SSD