From 78d15d9a12743e7cd4d2b10a734232711fcc3963 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 2 May 2025 13:19:01 +0530 Subject: [PATCH] drivers/intel/fsp2_0: Add Kconfig to select FSP for BMP rendering MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces `USE_COREBOOT_FOR_BMP_RENDERING`, a Kconfig option allowing platforms to choose coreboot to use its native bitmap (BMP) logo image rendering and skip using the FSP for this purpose during the boot process. By default this option is disabled (default 'n'), therefore, the FSP is utilized for displaying the BMP logo by populating the necessary FSP UPD parameters. Select this option for platforms that will use a coreboot native implementation for BMP rendering (note: the native coreboot rendering path is still under development/to be implemented). This Kconfig provides the switch for such future integration. Key changes: - A new boolean Kconfig `USE_COREBOOT_FOR_BMP_RENDERING` is added under `drivers/intel/fsp2_0/Kconfig`. It depends on `BMP_LOGO` and defaults to 'n'. - The help text clarifies that selecting this option will skip FSP-based BMP rendering. Deselection implies a fallback to the FSP based implementation. - The function `soc_load_logo`, previously responsible for populating FSP UPD parameters for the logo, is renamed to `soc_load_logo_by_fsp`. This clarifies its role is specific to FSP-driven logo display. - The call to `soc_load_logo_by_fsp` in `fsp2_0/silicon_init.c` is now conditional on `CONFIG(BMP_LOGO)` being enabled but the new `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)` remains disabled. - Implementations and calls to the renamed function are updated across relevant SoC directories (AMD Mendocino, Intel Alder Lake, Apollolake, Cannon Lake, Meteor Lake, Panther Lake, Skylake). This change offers platforms greater flexibility in managing BMP logo display, allowing them to either leverage FSP capabilities or integrate with coreboot's native methods as they become available. BUG=b:409718202 TEST=Built and booted google/fatcat. Verified boot splash was rendered by FSP as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `n`. Change-Id: Ieda085df02263b9bf4bdd8f5d0e2137bef75def9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/87513 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella --- src/drivers/intel/fsp2_0/Kconfig | 18 ++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/api.h | 7 +++++-- src/drivers/intel/fsp2_0/silicon_init.c | 11 +++++++---- src/soc/amd/mendocino/fsp_s_params.c | 2 +- src/soc/intel/alderlake/fsp_params.c | 2 +- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/cannonlake/fsp_params.c | 2 +- src/soc/intel/meteorlake/fsp_params.c | 2 +- src/soc/intel/pantherlake/fsp_params.c | 2 +- src/soc/intel/skylake/chip.c | 2 +- 10 files changed, 37 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 942591585d..715ec2a759 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -475,4 +475,22 @@ config BUILDING_WITH_DEBUG_FSP Enable this option if you are using a debug build of the FSP (Firmware Support Package) in your project. +config USE_COREBOOT_FOR_BMP_RENDERING + bool + default n + help + This option forces coreboot to use its native bitmap (BMP) image rendering + and skip using the FSP for this purpose during the boot process. + + If this option is selected (y), the platform will rely on the + coreboot native implementation for rendering BMP images. This might be + chosen if there are issues with FSP rendering or if native rendering + is preferred for specific reasons. + + If this option is not selected (n), the FSP's capabilities for BMP rendering + will be utilized. + + Platforms can choose to override this Kconfig option based on their + specific graphics requirements and FSP capabilities. + endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 0cbefbe9ae..8c9dc8c529 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -85,8 +85,11 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ void setup_mma(FSP_M_CONFIG *memory_cfg); -/* Update the SOC specific logo param and load the logo. */ -void soc_load_logo(FSPS_UPD *supd); +/* + * Populate UPD entries for the logo if the platform utilizes + * the FSP's capability for rendering bitmap (BMP) images. + */ +void soc_load_logo_by_fsp(FSPS_UPD *supd); /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index f3472420bc..cd4b5cb682 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -124,9 +124,12 @@ static void do_silicon_init(struct fsp_header *hdr) /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); - /* Populate logo related entries */ - if (CONFIG(BMP_LOGO)) - soc_load_logo(upd); + /* + * Populate UPD entries for the logo if the platform utilizes + * the FSP's capability for rendering bitmap (BMP) images. + */ + if (CONFIG(BMP_LOGO) && !CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)) + soc_load_logo_by_fsp(upd); /* Call SiliconInit */ silicon_init = (void *)(uintptr_t)(hdr->image_base + @@ -269,7 +272,7 @@ void fsp_silicon_init(void) fsp_display_timestamp(); } -__weak void soc_load_logo(FSPS_UPD *supd) { } +__weak void soc_load_logo_by_fsp(FSPS_UPD *supd) { } static void release_logo(void *arg_unused) { diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 5393eba911..23b2cfe5ce 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -59,7 +59,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) payload_preload(); } -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.logo_bmp_buffer = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 022b41e08a..a788319efc 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1381,7 +1381,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { struct soc_intel_common_config *config = chip_get_common_soc_structure(); FSP_S_CONFIG *s_cfg = &supd->FspsConfig; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ab5b5d884d..c5553780ea 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -914,7 +914,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 993efbb107..2e00018f36 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -801,7 +801,7 @@ __weak void mainboard_silicon_init_params(FSPS_UPD *supd) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.LogoPtr = (uintptr_t)bmp_load_logo(&logo_size); diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index a14d385ecf..30ea478432 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -871,7 +871,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { struct soc_intel_common_config *config = chip_get_common_soc_structure(); FSP_S_CONFIG *s_cfg = &supd->FspsConfig; diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index 32be2852db..f45d333032 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -800,7 +800,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { efi_uintn_t logo, blt_size; uint32_t logo_size; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 0356c3e8dd..0061c10ae8 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -511,7 +511,7 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) } /* Handle FSP logo params */ -void soc_load_logo(FSPS_UPD *supd) +void soc_load_logo_by_fsp(FSPS_UPD *supd) { size_t logo_size; supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size);