From 78ba87d6bec191833d201fef098a3db465664f7d Mon Sep 17 00:00:00 2001 From: Andrew Ip Date: Mon, 28 Oct 2002 14:05:30 +0000 Subject: [PATCH] updated to pci_find_device --- src/southbridge/via/vt8231/southbridge.c | 210 +++++++++++++++-------- 1 file changed, 135 insertions(+), 75 deletions(-) diff --git a/src/southbridge/via/vt8231/southbridge.c b/src/southbridge/via/vt8231/southbridge.c index 0afc57c676..61f4340714 100644 --- a/src/southbridge/via/vt8231/southbridge.c +++ b/src/southbridge/via/vt8231/southbridge.c @@ -1,29 +1,53 @@ #include #include #include +#include void keyboard_on() { volatile unsigned char regval; + struct pci_dev *dev; - /* pcibios_read_config_byte(0, 0x88, 0x51, ®val); */ - /*regval |= 0x01; */ + printk_debug("keyboard_on\n"); regval = 0xcf; - pcibios_write_config_byte(0, 0x88, 0x51, regval); + + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + if (dev) { + pci_write_config_byte(dev, 0x51, regval); + } /* disable USB1 */ - pcibios_write_config_byte(0, 0x8A, 0x3c, 0x00); - pcibios_write_config_byte(0, 0x8A, 0x04, 0x00); - pcibios_read_config_byte(0, 0x88, 0x50, ®val); - regval |= 0x10; - pcibios_read_config_byte(0, 0x88, 0x50, regval); + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); + if (dev) { + pci_write_config_byte(dev, 0x3c, 0x00); + } + if (dev) { + pci_write_config_byte(dev, 0x04, 0x00); + } + + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + if (dev) { + pci_read_config_byte(dev, 0x50, ®val); + regval |= 0x10; + pci_write_config_byte(dev, 0x50, regval); + } /* disable USB2 */ - pcibios_write_config_byte(0, 0x8B, 0x3c, 0x00); - pcibios_write_config_byte(0, 0x8B, 0x04, 0x00); - pcibios_read_config_byte(0, 0x88, 0x50, ®val); - regval |= 0x20; - pcibios_write_config_byte(0, 0x88, 0x50, regval); + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, \ + dev); + if (dev) { + pci_write_config_byte(dev, 0x3c, 0x00); + } + if (dev) { + pci_write_config_byte(dev, 0x04, 0x00); + } + + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + if (dev) { + pci_read_config_byte(dev, 0x50, ®val); + regval |= 0x20; + pci_write_config_byte(dev, 0x50, regval); + } pc_keyboard_init(); @@ -31,94 +55,130 @@ void keyboard_on() void nvram_on() { - /* the VIA 686A South has a very different nvram setup than the piix4e ... */ + /* the VIA 8231 South has a very different nvram setup than the piix4e ... */ /* turn on ProMedia nvram. */ /* TO DO: use the PciWriteByte function here. */ - pcibios_write_config_byte(0, 0x88, 0x41, 0xff); + + struct pci_dev *dev; + + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + if (dev) { + pci_write_config_byte(dev, 0x41, 0xc0); + } } void southbridge_fixup() { - unsigned int devfn; unsigned char enables; + struct pci_dev *dev; + struct pci_dev *dev0; + struct pci_dev dev_cpy; + unsigned int devfn; // enable the internal I/O decode - // to do: use the pcibios_find function here, instead of - // hard coding the devfn. - devfn = PCI_DEVFN(17, 0); - enables = pcibios_read_config_byte(0, devfn, 0x6C, &enables); - enables |= 0x80; - pcibios_write_config_byte(0, devfn, 0x6C, enables); + dev0 = 0; + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + if (dev) { + dev0 = dev; + memcpy(&dev_cpy, dev, sizeof(dev_cpy)); + pci_read_config_byte(dev, 0x6c, &enables); + enables |= 0x80; + pci_write_config_byte(dev, 0x6c, enables); + } else { + printk_debug("IDE pci_find_device function 0 failed\n"); + } #ifndef DISABLE_SOUTHBRIDGE_COM_PORTS // enable com1 and com2. - enables = pcibios_read_config_byte(0, devfn, 0x6e, &enables); - // 0x80 is enable com port b, 0x1 is to make it com2, 0x8 is enable com port a as com1 enables = 0x80 | 0x1 | 0x8 ; - pcibios_write_config_byte(0, devfn, 0x6e, enables); - // note: this is also a redo of some port of assembly, but we want everything up. + if (dev) { + pci_write_config_byte(dev, 0x6e, enables); + } + // note: this is also a redo of some port of assembly, but we + // want everything up. // set com1 to 115 kbaud // not clear how to do this yet. // forget it; done in assembly. #endif + // enable IDE, since Linux won't do it. // First do some more things to devfn (17,0) // note: this should already be cleared, according to the book. - pcibios_read_config_byte(0, devfn, 0x50, &enables); - printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); - enables &= ~8; // need manifest constant here! - printk_debug("set IDE reg. 50 to 0x%x\n", enables); - pcibios_write_config_byte(0, devfn, 0x50, enables); + if (dev) { + pci_read_config_byte(dev, 0x50, &enables); + printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk_debug("set IDE reg. 50 to 0x%x\n", enables); + pci_write_config_byte(dev, 0x50, enables); + } // set default interrupt values (IDE) - pcibios_read_config_byte(0, devfn, 0x4c, &enables); - printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. - enables &= ~0xf; - enables |= 4; - printk_debug("setting reg. 4c to 0x%x\n", enables); - pcibios_write_config_byte(0, devfn, 0x4c, enables); - + if (dev) { + pci_read_config_byte(dev, 0x4c, &enables); + printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk_debug("setting reg. 4c to 0x%x\n", enables); + pci_write_config_byte(dev, 0x4c, enables); + } + // set up the serial port interrupts. // com2 to 3, com1 to 4 - pcibios_write_config_byte(0, devfn, 0x46, 0x04); - pcibios_write_config_byte(0, devfn, 0x47, 0x03); - devfn = PCI_DEVFN(17, 1); - pcibios_read_config_byte(0, devfn, 0x40, &enables); - printk_debug("enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pcibios_write_config_byte(0, devfn, 0x40, enables); - pcibios_read_config_byte(0, devfn, 0x40, &enables); - printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + if (dev) { + pci_write_config_byte(dev, 0x46, 0x04); + pci_write_config_byte(dev, 0x47, 0x03); + } + + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0); + if (!dev) { + if (dev0) { + dev = &dev_cpy; + dev_cpy.devfn |= 1; + } + } + if (!dev) { + printk_debug("IDE pci_find_device function 1 failed\n"); + } else { + pci_read_config_byte(dev, 0x40, &enables); + printk_debug("enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config_byte(dev, 0x40, enables); + + pci_read_config_byte(dev, 0x40, &enables); + printk_debug("enables in reg 0x40 read back as 0x%x\n", \ + enables); + } + // address decoding. // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - pcibios_read_config_byte(0, devfn, 0x9, &enables); - printk_debug("enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - pcibios_write_config_byte(0, devfn, 0x9, enables); - pcibios_read_config_byte(0, devfn, 0x9, &enables); - printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. - pcibios_read_config_byte(0, devfn, 0x4, &enables); - printk_debug("command in reg 0x4 0x%x\n", enables); - enables |= 5; - pcibios_write_config_byte(0, devfn, 0x4, enables); - pcibios_read_config_byte(0, devfn, 0x4, &enables); - printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); - - // oh well, the PCI BARs don't work right. - // This chip will not work unless IDE runs at standard legacy - // values. - - pcibios_write_config_dword(0, devfn, 0x10, 0x1f1); - pcibios_write_config_dword(0, devfn, 0x14, 0x3f5); - pcibios_write_config_dword(0, devfn, 0x18, 0x171); - pcibios_write_config_dword(0, devfn, 0x1c, 0x375); - pcibios_write_config_dword(0, devfn, 0x20, 0xcc0); + if (dev) { + pci_read_config_byte(dev, 0x9, &enables); + printk_debug("enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + pci_write_config_byte(dev, 0x9, enables); + pci_read_config_byte(dev, 0x9, &enables); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + // standard bios sets master bit. + pci_read_config_byte(dev, 0x4, &enables); + printk_debug("command in reg 0x4 0x%x\n", enables); + enables |= 5; + pci_write_config_byte(dev, 0x4, enables); + pci_read_config_byte(dev, 0x4, &enables); + printk_debug("command in reg 0x4 reads back as 0x%x\n", \ + enables); + // oh well, the PCI BARs don't work right. + // This chip will not work unless IDE runs at standard legacy + // values. + pci_write_config_dword(dev, 0x10, 0x1f1); + pci_write_config_dword(dev, 0x14, 0x3f5); + pci_write_config_dword(dev, 0x18, 0x171); + pci_write_config_dword(dev, 0x1c, 0x375); + pci_write_config_dword(dev, 0x20, 0xcc0); + } }