From 770717b4333ca4584ffc7580e97ed30ea650a094 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 24 Aug 2015 17:43:07 -0700 Subject: [PATCH] veyron: sdram_config: Sync up Danger and add another sanity check I don't quite remember when we decided to add Danger to the firmware branch in the first place, but it looks like we did and we didn't bring all of its SDRAM configs with us from ToT. This patch syncs them back to where Jerry is, since they should be 100% identical. Also, this whole copy&pasting when cherry-picking SDRAM CLs makes me anxious... one line too few or too many removed could have very ugly consequences. Let's add another assertion to try to catch that should it ever happen. BRANCH=veyron BUG=None TEST=None Change-Id: I7c142b7d329733e3e5af7aac1e623437224a315e Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/295443 Reviewed-by: David Hendricks --- .../google/veyron_brain/sdram_configs.c | 1 + .../google/veyron_danger/sdram_configs.c | 23 +-- .../sdram_inf/sdram-ddr3-hynix-2GB.inc | 151 +++++++++--------- .../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 +++++++++ .../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 +++++++++ .../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 +++++++++ .../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 +++++++++ .../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 +++++++++ .../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 +++++++++ .../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 +++++++++ .../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 2 +- .../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 +++++++++ .../google/veyron_gus/sdram_configs.c | 1 + .../google/veyron_jaq/sdram_configs.c | 1 + .../google/veyron_jerry/sdram_configs.c | 1 + .../google/veyron_mickey/sdram_configs.c | 1 + .../google/veyron_mighty/sdram_configs.c | 1 + .../google/veyron_minnie/sdram_configs.c | 1 + .../google/veyron_nicky/sdram_configs.c | 1 + .../google/veyron_pinky/sdram_configs.c | 1 + .../google/veyron_romy/sdram_configs.c | 1 + .../google/veyron_speedy/sdram_configs.c | 1 + .../google/veyron_thea/sdram_configs.c | 1 + 23 files changed, 723 insertions(+), 87 deletions(-) create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-2GB.inc create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-4GB.inc create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc create mode 100644 src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc diff --git a/src/mainboard/google/veyron_brain/sdram_configs.c b/src/mainboard/google/veyron_brain/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_brain/sdram_configs.c +++ b/src/mainboard/google/veyron_brain/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_danger/sdram_configs.c b/src/mainboard/google/veyron_danger/sdram_configs.c index b8bd2db41a..9c17ce75a8 100644 --- a/src/mainboard/google/veyron_danger/sdram_configs.c +++ b/src/mainboard/google/veyron_danger/sdram_configs.c @@ -26,22 +26,23 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ +#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */ +#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */ +#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ +#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ +#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc index 07161c0dfa..659cfd4b88 100644 --- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc @@ -1,77 +1,78 @@ { - { - { - .rank = 0x1, - .col = 0xA, - .bk = 0x3, - .bw = 0x2, - .dbw = 0x1, - .row_3_4 = 0x0, - .cs0_row = 0xF, - .cs1_row = 0xF - }, - { - .rank = 0x1, - .col = 0xA, - .bk = 0x3, - .bw = 0x2, - .dbw = 0x1, - .row_3_4 = 0x0, - .cs0_row = 0xF, - .cs1_row = 0xF - } - }, - { - .togcnt1u = 0x215, - .tinit = 0xC8, - .trsth = 0x1F4, - .togcnt100n = 0x35, - .trefi = 0x4E, - .tmrd = 0x4, - .trfc = 0xBB, - .trp = 0x8, - .trtw = 0x4, - .tal = 0x0, - .tcl = 0x8, - .tcwl = 0x6, - .tras = 0x14, - .trc = 0x1D, - .trcd = 0x8, - .trrd = 0x6, - .trtp = 0x4, - .twr = 0x8, - .twtr = 0x4, - .texsr = 0x200, - .txp = 0x4, - .txpdll = 0xD, - .tzqcs = 0x40, - .tzqcsi = 0x0, - .tdqs = 0x1, - .tcksre = 0x6, - .tcksrx = 0x6, - .tcke = 0x4, - .tmod = 0xC, - .trstl = 0x36, - .tzqcl = 0x100, - .tmrr = 0x0, - .tckesr = 0x5, - .tdpd = 0x0 - }, - { - .dtpr0 = 0x3AD48890, - .dtpr1 = 0xBB08D8, - .dtpr2 = 0x1002B600, - .mr[0] = 0x840, - .mr[1] = 0x40, - .mr[2] = 0x8, - .mr[3] = 0x0 - }, - .noc_timing = 0x2891E41D, - .noc_activate = 0x5B6, - .ddrconfig = 3, - .ddr_freq = 533*MHz, - .dramtype = DDR3, - .num_channels = 2, - .stride = 9, - .odt = 1 + /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 }, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc new file mode 100644 index 0000000000..9f2ca8a7d2 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Hynix H5TC8G63xxx chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 13, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc new file mode 100644 index 0000000000..bd82e7b774 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Nanya NT5CC256M16DP chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc new file mode 100644 index 0000000000..a32f1a6129 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Samsung K4B8G1646Q chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 13, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-2GB.inc new file mode 100644 index 0000000000..ef82b27781 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two ELPIDA F8132A3MA-GD-F chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0 +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-4GB.inc new file mode 100644 index 0000000000..e071646bf4 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-elpida-4GB.inc @@ -0,0 +1,78 @@ +{ + /* two ELPIDA FA232A2MA-GC-F chips */ + { + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 6, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0 +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc new file mode 100644 index 0000000000..00dc549161 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Hynix H9CCNNN8GTMLAR chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc new file mode 100644 index 0000000000..a48ac42a0e --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB.inc index f42f1b1b8b..0f15ba5074 100644 --- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -74,5 +74,5 @@ .dramtype = LPDDR3, .num_channels = 2, .stride = 9, - .odt = 1 + .odt = 0, }, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc new file mode 100644 index 0000000000..09d260bc23 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 6, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_gus/sdram_configs.c b/src/mainboard/google/veyron_gus/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_gus/sdram_configs.c +++ b/src/mainboard/google/veyron_gus/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_jaq/sdram_configs.c b/src/mainboard/google/veyron_jaq/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_jaq/sdram_configs.c +++ b/src/mainboard/google/veyron_jaq/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_jerry/sdram_configs.c +++ b/src/mainboard/google/veyron_jerry/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_mighty/sdram_configs.c b/src/mainboard/google/veyron_mighty/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_mighty/sdram_configs.c +++ b/src/mainboard/google/veyron_mighty/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_minnie/sdram_configs.c b/src/mainboard/google/veyron_minnie/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_minnie/sdram_configs.c +++ b/src/mainboard/google/veyron_minnie/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_nicky/sdram_configs.c b/src/mainboard/google/veyron_nicky/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_nicky/sdram_configs.c +++ b/src/mainboard/google/veyron_nicky/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_romy/sdram_configs.c +++ b/src/mainboard/google/veyron_romy/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_speedy/sdram_configs.c +++ b/src/mainboard/google/veyron_speedy/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() { diff --git a/src/mainboard/google/veyron_thea/sdram_configs.c b/src/mainboard/google/veyron_thea/sdram_configs.c index 4a1831b80f..49d1aba43a 100644 --- a/src/mainboard/google/veyron_thea/sdram_configs.c +++ b/src/mainboard/google/veyron_thea/sdram_configs.c @@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!"); const struct rk3288_sdram_params *get_sdram_config() {