support for new boards and chips and cpus
This commit is contained in:
Ronald G. Minnich
parent
14342bf376
commit
7699e7a8f9
29 changed files with 7973 additions and 0 deletions
115
src/include/cpu/stpc/consumer2/stpc.h
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115
src/include/cpu/stpc/consumer2/stpc.h
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#ifndef ROM_STPC_H
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#define ROM_STPC_H
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/*
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* Bootstrap code for the STPC Consumer II
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*
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* by Steve M. Gehlbach
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*
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* orig by: johryd
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*
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*
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*/
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/*
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* framebuffer size
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*/
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#define STPC_FRAME_BUF_SZ 512 /* size in kb, will be divided with 128 */
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/*
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* SIP configration registers:
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*/
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#define STPC_CONF_REG_INDEX 0x22
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#define STPC_CONF_REG_DATA 0x23
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/*
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* DRAM types:
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*/
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#define STPC_DRAM_FPM_60 0
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#define STPC_DRAM_FPM_70 1
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#define STPC_DRAM_EDO_60 2
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#define STPC_DRAM_EDO_70 3
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#define STPC_DRAM_SDRAM 4
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/*
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* Macro: stpc_conf_write_macro
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* Prototype: value = stpc_conf_write_macro(reg, data)
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* %al %ah %al
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*/
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#define stpc_conf_write_macro \
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xchgb %ah, %al ;\
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outb %al, $STPC_CONF_REG_INDEX ;\
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xchgb %ah, %al ;\
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outb %al, $STPC_CONF_REG_DATA
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/*
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* Macro: stpc_conf_read_macro
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* Prototype: value = stpc_conf_write_read(reg)
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* %al %ah
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*/
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#define stpc_conf_read_macro \
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xchgb %ah, %al ;\
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outb %al, $STPC_CONF_REG_INDEX ;\
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xchgb %ah, %al ;\
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inb $STPC_CONF_REG_DATA, %al
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/*
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* Macro: stpc_chip_getbusspeed_macro
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* Prototype: value = stpc_chip_getbusspeed()
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* %al
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* Trashed: %ah, %al
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*/
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#define stpc_chip_getbusspeed_macro \
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movb $0x5f, %ah ;\
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stpc_conf_read_macro ;\
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andb $0b00111000, %al ;\
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shrb $3, %al
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/*
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* Macro: stpc_outb_macro
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* Prototype: stpc_outb_macro(value, port)
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* Trashed: %al
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*/
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#define stpc_outb_macro(value,port) \
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movb $(value), %al ;\
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outb %al, $(port)
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/*
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* Macro: stpc_chip_post_macro
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* Prototype: stpc_chip_post(value)
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* Trashed: %al
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*/
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#define stpc_chip_post_macro(value) \
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movb $(value), %al ;\
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outb %al, $0x80
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/*
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* Macro: stpc_delay_macro
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* Prototype: stpc_delay_macro(value)
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* Trashed: %ecx, %al
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*/
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#define stpc_delay_macro(value) \
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movl $value, %ecx ;\
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0: inb $0x80, %al ;\
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loop 0b
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/*
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* Sets all of the mem regs from %bh to 0x33 to
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* the value in %al
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* Macro: stpc_set_memreg_macro
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* Prototype: stpc_set_memreg_macro
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* Input: %bh: first mem reg to set (0x30-0x33)
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* %al: setting for all the registers
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* Trashed: %ah
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*/
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#define stpc_set_memreg_macro \
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movb %bh, %ah ;\
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0: ;\
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stpc_conf_write_macro ;\
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inc %ah ;\
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cmpb $0x33, %ah ;\
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jbe 0b
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#endif /* ROM_STPC_H */
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35
src/include/cpu/stpc/consumer2/vga_stpc.h
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35
src/include/cpu/stpc/consumer2/vga_stpc.h
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/*
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* by
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* Steve M. Gehlbach
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* for stpc consumer II
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*/
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//
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// STPC extended registers, non-standard
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// must write 57h to seq reg 6 to access these
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// must be done individually, not in par array
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#define CRTC_REPAINT_C0 0x19
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#define CRTC_REPAINT_C1 0x1A
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#define CRTC_REPAINT_C2 0x1B
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#define CRTC_REPAINT_C3 0x1C
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#define CRTC_PAGE_R0 0x1D
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#define CRTC_PAGE_R1 0x1E
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#define CRTC_GE_ENABLE 0x1F
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#define CRTC_GE_GBASE 0x20
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#define CRTC_GE_APER 0x21
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#define CRTC_REPAINT_C4 0x25
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#define CRTC_REPAINT_C5 0x27
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#define CRTC_PALLETTE_C 0x28
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#define CRTC_URGENT_START 0x33
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#define CRTC_DISP_YOFFS_L 0x34
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#define CRTC_DISP_YOFFS_H 0x35
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#define CRTC_GV_R 0x3B
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// these are read only for STPC, no settings
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#define CRTC_GCD_R 0x22
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#define CRTC_AA_FF_R 0x24
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#define CRTC_AI_R 0x26
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// not in automatic list; has to be done manual
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#define SEQ_XREG_UNLOCK 0x06
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228
src/include/pc80/vga.h
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228
src/include/pc80/vga.h
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/*
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*
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* modified
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* by Steve M. Gehlbach <steve@kesa.com>
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*
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* Originally from linux/drivers/video/vga16.c by
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* Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
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* Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
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* Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
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* Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
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*
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*/
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#ifndef VGA_H_INCL
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#define VGA_H_INCL 1
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#include <cpu/p5/io.h>
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#define u8 unsigned char
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#define u16 unsigned short
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#define u32 unsigned int
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#define __u32 u32
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#define VERROR -1
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#define CHAR_HEIGHT 16
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#define LINES 25
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#define COLS 80
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// macros for writing to vga regs
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#define write_crtc(data,addr) outb(addr,CRT_IC); outb(data,CRT_DC)
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#define write_att(data,addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80)
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#define write_seq(data,addr) outb(addr,SEQ_I); outb(data,SEQ_D)
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#define write_gra(data,addr) outb(addr,GRA_I); outb(data,GRA_D)
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u8 read_seq_b(u16 addr);
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u8 read_gra_b(u16 addr);
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u8 read_crtc_b(u16 addr);
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u8 read_att_b(u16 addr);
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#ifdef VGA_HARDWARE_FIXUP
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void vga_hardware_fixup(void);
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#else
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#define vga_hardware_fixup() do{} while(0)
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#endif
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#define SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
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#define SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
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#define SYNC_EXT 4 /* external sync */
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#define SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
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#define SYNC_BROADCAST 16 /* broadcast video timings */
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/* vtotal = 144d/288n/576i => PAL */
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/* vtotal = 121d/242n/484i => NTSC */
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#define SYNC_ON_GREEN 32 /* sync on green */
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#define VMODE_NONINTERLACED 0 /* non interlaced */
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#define VMODE_INTERLACED 1 /* interlaced */
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#define VMODE_DOUBLE 2 /* double scan */
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#define VMODE_MASK 255
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#define VMODE_YWRAP 256 /* ywrap instead of panning */
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#define VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
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#define VMODE_CONUPDATE 512 /* don't update x/yoffset */
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/* VGA data register ports */
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#define CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
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#define CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
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#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */
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#define GRA_D 0x3CF /* Graphics Controller Data Register */
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#define SEQ_D 0x3C5 /* Sequencer Data Register */
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#define MIS_R 0x3CC // Misc Output Read Register
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#define MIS_W 0x3C2 // Misc Output Write Register
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#define IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
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#define IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
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#define PEL_D 0x3C9 /* PEL Data Register */
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#define PEL_MSK 0x3C6 /* PEL mask register */
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/* EGA-specific registers */
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#define GRA_E0 0x3CC /* Graphics enable processor 0 */
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#define GRA_E1 0x3CA /* Graphics enable processor 1 */
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/* VGA index register ports */
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#define CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
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#define CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
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#define ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
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#define GRA_I 0x3CE /* Graphics Controller Index */
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#define SEQ_I 0x3C4 /* Sequencer Index */
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#define PEL_IW 0x3C8 /* PEL Write Index */
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#define PEL_IR 0x3C7 /* PEL Read Index */
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/* standard VGA indexes max counts */
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#define CRTC_C 25 /* 25 CRT Controller Registers sequentially set*/
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// the remainder are not in the par array
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#define ATT_C 21 /* 21 Attribute Controller Registers */
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#define GRA_C 9 /* 9 Graphics Controller Registers */
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#define SEQ_C 5 /* 5 Sequencer Registers */
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#define MIS_C 1 /* 1 Misc Output Register */
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#define CRTC_H_TOTAL 0
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#define CRTC_H_DISP 1
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#define CRTC_H_BLANK_START 2
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#define CRTC_H_BLANK_END 3
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#define CRTC_H_SYNC_START 4
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#define CRTC_H_SYNC_END 5
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#define CRTC_V_TOTAL 6
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#define CRTC_OVERFLOW 7
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#define CRTC_PRESET_ROW 8
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#define CRTC_MAX_SCAN 9
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#define CRTC_CURSOR_START 0x0A
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#define CRTC_CURSOR_END 0x0B
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#define CRTC_START_HI 0x0C
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#define CRTC_START_LO 0x0D
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#define CRTC_CURSOR_HI 0x0E
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#define CRTC_CURSOR_LO 0x0F
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#define CRTC_V_SYNC_START 0x10
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#define CRTC_V_SYNC_END 0x11
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#define CRTC_V_DISP_END 0x12
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#define CRTC_OFFSET 0x13
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#define CRTC_UNDERLINE 0x14
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#define CRTC_V_BLANK_START 0x15
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#define CRTC_V_BLANK_END 0x16
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#define CRTC_MODE 0x17
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#define CRTC_LINE_COMPARE 0x18
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#define ATC_MODE 0x10
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#define ATC_OVERSCAN 0x11
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#define ATC_PLANE_ENABLE 0x12
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#define ATC_PEL 0x13
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#define ATC_COLOR_PAGE 0x14
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#define SEQ_CLOCK_MODE 0x01
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#define SEQ_PLANE_WRITE 0x02
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#define SEQ_CHARACTER_MAP 0x03
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#define SEQ_MEMORY_MODE 0x04
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#define GDC_SR_VALUE 0x00
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#define GDC_SR_ENABLE 0x01
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#define GDC_COMPARE_VALUE 0x02
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#define GDC_DATA_ROTATE 0x03
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#define GDC_PLANE_READ 0x04
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#define GDC_MODE 0x05
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#define GDC_MISC 0x06
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#define GDC_COMPARE_MASK 0x07
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#define GDC_BIT_MASK 0x08
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// text attributes
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#define VGA_ATTR_CLR_RED 0x4
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#define VGA_ATTR_CLR_GRN 0x2
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#define VGA_ATTR_CLR_BLU 0x1
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#define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)
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#define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
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#define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)
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#define VGA_ATTR_CLR_BLK 0
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#define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
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#define VGA_ATTR_BNK 0x80
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#define VGA_ATTR_ITN 0x08
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/*
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* vga register parameters
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* these are copied to the
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* registers.
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*
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*/
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struct vga_par {
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u8 crtc[CRTC_C];
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u8 atc[ATT_C];
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u8 gdc[GRA_C];
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u8 seq[SEQ_C];
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u8 misc; // the misc register, MIS_W
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u8 vss;
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};
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/* Interpretation of offset for color fields: All offsets are from the right,
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* inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
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* can use the offset as right argument to <<). A pixel afterwards is a bit
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* stream and is written to video memory as that unmodified. This implies
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* big-endian byte order if bits_per_pixel is greater than 8.
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*/
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struct fb_bitfield {
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__u32 offset; /* beginning of bitfield */
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__u32 length; /* length of bitfield */
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__u32 msb_right; /* != 0 : Most significant bit is */
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/* right */
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};
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struct screeninfo {
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__u32 xres; /* visible resolution */
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__u32 yres;
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__u32 xres_virtual; /* virtual resolution */
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__u32 yres_virtual;
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__u32 xoffset; /* offset from virtual to visible */
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__u32 yoffset; /* resolution */
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__u32 bits_per_pixel; /* guess what */
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__u32 grayscale; /* != 0 Graylevels instead of colors */
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struct fb_bitfield red; /* bitfield in fb mem if true color, */
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struct fb_bitfield green; /* else only length is significant */
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struct fb_bitfield blue;
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struct fb_bitfield transp; /* transparency */
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__u32 nonstd; /* != 0 Non standard pixel format */
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__u32 activate; /* see FB_ACTIVATE_* */
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__u32 height; /* height of picture in mm */
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__u32 width; /* width of picture in mm */
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__u32 accel_flags; /* acceleration flags (hints) */
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/* Timing: All values in pixclocks, except pixclock (of course) */
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__u32 pixclock; /* pixel clock in ps (pico seconds) */
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__u32 left_margin; /* time from sync to picture */
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__u32 right_margin; /* time from picture to sync */
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__u32 upper_margin; /* time from sync to picture */
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__u32 lower_margin;
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__u32 hsync_len; /* length of horizontal sync */
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__u32 vsync_len; /* length of vertical sync */
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__u32 sync; /* sync polarity */
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__u32 vmode; /* interlaced etc */
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__u32 reserved[6]; /* Reserved for future compatibility */
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};
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#endif
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