From 7673faea713d0ff483cb14b9769e0481867362dc Mon Sep 17 00:00:00 2001 From: Tongtong Pan Date: Wed, 22 Jan 2025 14:04:21 +0800 Subject: [PATCH] mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd Modify the overridetree.cb configuration to make the SSD effective. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I5d9219e0964ce1f2c8be6a37f93ead04943421d9 Signed-off-by: Tongtong Pan Reviewed-on: https://review.coreboot.org/c/coreboot/+/86098 Tested-by: build bot (Jenkins) Reviewed-by: Weimin Wu Reviewed-by: Subrata Banik --- src/mainboard/google/fatcat/variants/felino/overridetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 28072d5c10..d401ed2c63 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -184,13 +184,13 @@ chip soc/intel/pantherlake device ref pcie_rp9 on register "pcie_rp[PCIE_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, + .clk_src = 0, + .clk_req = 0, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "is_storage" = "true" - register "srcclk_pin" = "1" + register "srcclk_pin" = "0" device generic 0 on end end end # Gen5 SSD